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Montiel Nelson, Juan Antonio

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Title Issue Date
System for the integration of graphical parcel information in the urban cadastral database file Rubio Royo, E. ; Padron Hdez, J. M.; Montiel-Nelson, J. A. Issued date: 1991 Source: Environment & Planning B: Planning & Design,v. 18, p. 3-6 Artículo
High performance asynchronous FIR filter design in gaAs Montiel-Nelson, J. A. ; Nooshabadi, S. V. Issued date: 1997 DOI: 10.1049/ip-cds:19971324 Source: IEE Proceedings: Circuits, Devices and Systems[ISSN 1350-2409],v. 144, p. 289-296 JCR: 0,254 - Q3 Artículo
OLYMPO: A GaAs compiler for VLSI design Montiel-Nelson, J. A. ; de Armas, V. ; Sarmiento, R. ; Nunez, A. Issued date: 1998 Source: Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems,v. 3, p. 385-388 Artículo
A CORDIC processor for FFT computation and its implementation using gallium arsenide technology Sarmiento, R ; Tobajas, Félix ; De Armas Sosa, Valentín ; Esper-Chaín, Roberto ; López Feliciano, José Francisco , et al Issued date: 1998 DOI: 10.1109/92.661241 Source: Ieee Transactions On Very Large Scale Integration (Vlsi) Systems[ISSN 1063-8210],v. 6 (1), p. 18-30 JCR: 0,733 - Q1 SCIE Artículo
RME: Red Multi-LAN Experimental para Contenidos Multimedia Montiel Nelson, Juan Antonio Issued date: 2000 Source: BIT. Boletín informativo de telecomunicación [ISSN 0210-3923], n. 124, p. 74-75 Artículo
ATM over SDH: Design of a STM-16c transceiver using GaAs technology Tubío, O.; Esper-Chaín, R. ; González, F.; Tobajas, F. ; De Armas Sosa, Valentín , et al Issued date: 2002 DOI: 10.1016/S0026-2692(02)00115-5 Source: Microelectronics Journal[ISSN 0026-2692],v. 33, p. 1097-1105 JCR: 0,457 - Q3 SCIE Artículo
Multiplexer model for RTL satisfiability using MILP Navarro Botello,Héctor ; Montiel-Nelson, J. A. ; Sosa, J. ; García, J. C. ; Fay, D. Q M Issued date: 2004 DOI: 10.1049/el:20040304 Source: Electronics Letters[ISSN 0013-5194],v. 40, p. 417-418 SJR: 0,83 - Q1 JCR: 0,968 - Q2 SCIE Artículo
Fast feedthrough logic: A high performance logic family for GaAs Nooshabadi, Saeid; Montiel-Nelson, Juan A. Issued date: 2004 DOI: 10.1109/TCSI.2004.836840 Source: IEEE Transactions on Circuits and Systems I: Regular Papers[ISSN 1057-7122],v. 51, p. 2189-2203 JCR: 0,933 - Q2 Artículo
A Single-Capacitor Bootstrapped Power-Efficient CMOS Driver Garcia, J. C. ; Nooshabadi, Saeid; Montiel-Nelson, Juan A. Issued date: 2006 DOI: 10.1109/TCSII.2006.880337 Source: IEEE Transactions on Circuits and Systems II: Express Briefs[ISSN 1549-7747],v. 53, p. 877-881 SCIE Artículo
Low power and high performance arithmetic circuits in feedthrough CMOS logic family for low power applications Navarro-Botello, Victor ; Montiel-Nelson, Juan A. ; Nooshabadi, Saeid Issued date: 2006 DOI: 10.1166/jolpe.2006.066 Source: Journal of Low Power Electronics [ISSN 1546-1998], v. 2 (2), p. 300-307, 2006 ESCI Artículo
DB-driver: A low power CMOS bootstrapped differential cross-coupled driver García, J. C. ; Montiel-Nelson, J. A. ; Nooshabadi, S. Issued date: 2007 DOI: 10.1080/00207210701523363 Source: International Journal of Electronics[ISSN 0020-7217],v. 94, p. 809-819 JCR: 0,377 - Q3 SCIE Artículo
High performance low power CMOS dynamic logic for arithmetic circuits Navarro-Botello, Victor ; Montiel-Nelson, Juan A. ; Nooshabadi, Saeid Issued date: 2007 DOI: 10.1016/j.mejo.2007.03.018 Source: Microelectronics Journal[ISSN 0026-2692],v. 38, p. 482-488 JCR: 0,609 - Q3 SCIE Artículo
Analysis of High-Performance Fast Feedthrough Logic Families in CMOS Navarro-Botello, Victor ; Montiel-Nelson, Juan A. ; Nooshabadi, Saeid Issued date: 2007 DOI: 10.1109/TCSII.2007.891759 Source: IEEE Transactions on Circuits and Systems II: Express Briefs[ISSN 1549-7747],v. 54, p. 489-493 JCR: 1,104 - Q2 SCIE Artículo
Adder model for mixed integer linear programming Navarro Botello,Héctor ; Nooshabadi, S.; Montiel-Nelson, J. A. Issued date: 2009 DOI: 10.1049/el.2009.3637 Source: Electronics Letters[ISSN 0013-5194],v. 45, p. 348-349 SJR: 0,665 - Q1 JCR: 0,97 - Q3 SCIE Artículo
CMOS driver-receiver pair for low-swing signaling for low energy on-chip interconnects García Montesdeoca, José C.; Montiel-Nelson, Juan A. ; Nooshabadi, Saeid Issued date: 2009 DOI: 10.1109/TVLSI.2008.2004549 Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems[ISSN 1063-8210],v. 17, p. 311-316 JCR: 1,01 - Q2 SCIE Artículo
CMOS design and analysis of low-voltage signaling methodology for energy efficient on-chip interconnects García, José C. ; Montiel-Nelson, Juan A. ; Nooshabadi, Saeid Issued date: 2009 DOI: 10.1016/j.mejo.2008.12.003 Source: Microelectronics Journal[ISSN 0026-2692],v. 40, p. 1571-1581 JCR: 0,778 - Q3 SCIE Artículo
Application of genetic algorithm in computing the tradeoffs between power consumption versus delay in digital integrated circuit design Sosa, J. ; Montiel-Nelson, Juan A. ; Nooshabadi, Saeid Issued date: 2010 DOI: 10.1016/j.mejo.2010.01.010 Source: Microelectronics Journal[ISSN 0026-2692],v. 41, p. 135-141 JCR: 0,789 - Q3 SCIE Artículo
A genetic algorithm methodology to find the maximum datapath coverage for combinational logic circuits Sosa, Javier ; Montiel-Nelson, Juan A. ; Nooshabadi, Saeid Issued date: 2010 DOI: 10.1142/S0218126610006165 Source: Journal of Circuits, Systems and Computers[ISSN 0218-1266],v. 19, p. 435-450 JCR: 0,215 - Q4 SCIE Artículo
Electro-quasistatic analysis of an electrostatic induction micromotor using the cell method Monzón-Verona, José Miguel ; Santana-Martín, Francisco Jorge; Garcia-Alonso Montoya, Santiago ; Montiel-Nelson, Juan Antonio Issued date: 2010 DOI: 10.3390/s101009102 Source: Sensors (Switzerland)[ISSN 1424-8220],v. 10, p. 9102-9117 JCR: 1,774 - Q3 SCIE Artículo
Application of mixed integer linear programming in the generation of vectors with maximum datapath coverage for combinational logic circuits Sosa, Javier ; Montiel-Nelson, Juan A. ; Garcia-Montesdeoca, Jose C. ; Nooshabadi, Saeid Issued date: 2010 DOI: 10.1142/S0218126610006785 Source: Journal of Circuits, Systems and Computers[ISSN 0218-1266],v. 19, p. 1497-1516 JCR: 0,215 - Q4 SCIE Artículo