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Title: High performance low power CMOS dynamic logic for arithmetic circuits
Authors: Navarro-Botello, Victor 
Montiel-Nelson, Juan A. 
Nooshabadi, Saeid
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: Dynamic logic
CMOS digital integrated circuits
CMOS logic circuits
Low power arithmetic circuits
High speed arithmetic circuits
Issue Date: 2007
Publisher: 0026-2692
Journal: Microelectronics 
Abstract: This paper presents the design of high performance and low power arithmetic circuits using a new CMOS dynamic logic family, and analyzes its sensitivity against technology parameters for practical applications. The proposed dynamic logic family allows for a partial evaluation in a computational block before its input signals are valid, and quickly performs a final evaluation as soon as the inputs arrive. The proposed dynamic logic family is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. Furthermore, circuits based on the proposed concept perform better in high fanout and high switching frequencies due to both lower delay and dynamic power consumption. Experimental results, for practical circuits, demonstrate that low power feature of the propose dynamic logic provides for smaller propagation time delay (3.5 times), lower energy consumption (55%), and similar combined delay, power consumption and active area product (only 8% higher), while exhibiting lower sensitivity to power supply, temperature, capacitive load and process variations than the dynamic domino CMOS technologies.
ISSN: 0026-2692
DOI: 10.1016/j.mejo.2007.03.018
Source: Microelectronics Journal[ISSN 0026-2692],v. 38, p. 482-488
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