Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/49656
Title: CMOS design and analysis of low-voltage signaling methodology for energy efficient on-chip interconnects
Authors: García, José C. 
Montiel-Nelson, Juan A. 
Nooshabadi, Saeid
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: Digital CMOS
Low-voltage
low-energy
Interconnect signaling
Level converters, et al
Issue Date: 2009
Publisher: 0026-2692
Journal: Microelectronics 
Conference: International Conference on Microelectronics 
Abstract: This paper provides a comparative study of the low-voltage signaling methodologies in terms of delay, energy dissipation, and energy delay product (energy x delay), and sensitivity technology process variations, and noise. We also present the design of two symmetric low-swing driver-receiver pairs for driving signals on the global interconnect lines. The key advantage of the proposed signaling schemes is that they require only one power supply and threshold voltage, hence significantly reducing the design complexity. The proposed signaling schemes were implemented on 1.0 V 0.13 mu m CMOS technology, for signal transmission along a wire-length of 10 mm. When compared with other counterpart symmetric and asymmetric low-swing signaling schemes, the proposed schemes perform better in terms of delay, energy dissipation and energy x delay.
URI: http://hdl.handle.net/10553/49656
ISSN: 0026-2692
DOI: 10.1016/j.mejo.2008.12.003
Source: Microelectronics Journal[ISSN 0026-2692],v. 40, p. 1571-1581
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