Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/49650
Title: Application of genetic algorithm in computing the tradeoffs between power consumption versus delay in digital integrated circuit design
Authors: Sosa, J. 
Montiel-Nelson, Juan A. 
Nooshabadi, Saeid
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: Power optimization
Gate sizing
Tradeoff curve
Genetic algorithms
Linear programming
Issue Date: 2010
Publisher: 0026-2692
Journal: Microelectronics 
Abstract: This paper presents a novel methodology to obtain the entire power consumption versus delay tradeoff curve for the critical paths of a combinational logic circuit in a very efficient way using the genetic algorithm (GA). In order to evaluate the proposed algorithm the most representative set of two-level and multi-level networks from the MCNC91 benchmark suite were processed. The required computational effort, measured in terms of CPU time, is several times better for the proposed GA optimization technique than liner programming (LP) technique. On the other hand, the optimal design points obtained by the GA and LP techniques are very close to each other to within 0.3%.
URI: http://hdl.handle.net/10553/49650
ISSN: 0026-2692
DOI: 10.1016/j.mejo.2010.01.010
Source: Microelectronics Journal[ISSN 0026-2692],v. 41, p. 135-141
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