Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/49687
Title: Fast feedthrough logic: A high performance logic family for GaAs
Authors: Nooshabadi, Saeid
Montiel-Nelson, Juan A. 
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: Digital arithmetic circuits
gallium arsenide integrated circuit
Latches
register based sequential circuits
standard cell-based design
Issue Date: 2004
Publisher: 1057-7122
Journal: IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 
Abstract: A GaAs dynamic logic family using the feedthrough evaluation concept is presented in this paper. Feedthrough logic (FTL) allows the outputs to be partially generated before the input signals arrive. A modified version of this logic, where the function and its complement are implemented in a differential structure, is also introduced. In an FTL gate, the logic outputs are reset to low during the high phase of the clock and evaluated during the low phase of the clock. Resetting to low alleviates the problems of charge sharing and leakage current associated with the other GaAs dynamic logic families. FTL logic functions can be cascaded in a domino-like fashion without a need for the intervening inverters. We employ this novel concept to design several arithmetic circuits. We compare a 4-bit ripple carry adder in FTL with the other published works in terms of device count, area, delay, clock rate and power consumption. The results demonstrate that FTL is the simplest, the fastest, and consumes least power. In addition, our FTL design compares very well with the standard CMOS technology. FTL gates are fully compatible with direct coupled field-effect transitor logic (DCFL), and therefore, can be included in a DCFL standard cell library for improving cell-based ASIC performance. To match the high-speed of the FTL combinational blocks, we present a single-ended latch for pipelining the FTL blocks. Comparisons with the other published results demonstrate the superior performance of our dynamic latch.
URI: http://hdl.handle.net/10553/49687
ISSN: 1057-7122
DOI: 10.1109/TCSI.2004.836840
Source: IEEE Transactions on Circuits and Systems I: Regular Papers[ISSN 1057-7122],v. 51, p. 2189-2203
Appears in Collections:Artículos
Show full item record

SCOPUSTM   
Citations

16
checked on Jul 25, 2021

WEB OF SCIENCETM
Citations

13
checked on Jul 25, 2021

Page view(s)

14
checked on Jul 24, 2021

Google ScholarTM

Check

Altmetric


Share



Export metadata



Items in accedaCRIS are protected by copyright, with all rights reserved, unless otherwise indicated.