High performance asynchronous FIR filter design in gaAs

Abstract

An asynchronous FIR architecture design using a mixed mode logic approach in GaAs technology is presented. Combining an asynchronous design style with static and dynamic logic proves to be very suitable for high speed and low power implementation of real time mobile computing applications. The authors introduce a novel clocked dynamic latched (CDL) logic in GaAs to implement the micropipeline latches required in the single phase signalling. The reliable implementation of an 11-tap FIR filter in terms of speed, area and power dissipation in GaAs MESFET 0.6 mu m Vitesse technology is demonstrated. This ASIC system is fully operative across the full range of process spread variations and the temperature range of 0 to 100 degrees C. It is robust against power supply variations of 15%.