Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/76792
Title: Low power and high performance arithmetic circuits in feedthrough CMOS logic family for low power applications
Authors: Navarro-Botello, Victor 
Montiel-Nelson, Juan A. 
Nooshabadi, Saeid
UNESCO Clasification: 2203 Electrónica
Keywords: Feedthrough logic
Low power arithmetic circuits
High speed CMOS techniques
Issue Date: 2006
Journal: Journal of Low Power Electronics 
Abstract: This paper presents the design of low power high performance arithmetic circuits using the feedthrough logic (FTL) 1 concept. FTL is ideally suited for the circuit design where the critical path is made of a large cascade of inverting gates. Its high fanout and high switching frequencies are due to both lower delay and dynamic power consumption. Low power FTL arithmetic circuits provides for smaller propagation delay time (2.6 times), lower energy consumption (31%), and similar combined delay, power consumption, and active area product, when compared with the standard CMOS technologies.
URI: http://hdl.handle.net/10553/76792
ISSN: 1546-1998
DOI: 10.1166/jolpe.2006.066
Source: Journal of Low Power Electronics [ISSN 1546-1998], v. 2 (2), p. 300-307, 2006
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