Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/76792
DC FieldValueLanguage
dc.contributor.authorNavarro-Botello, Victoren_US
dc.contributor.authorMontiel-Nelson, Juan A.en_US
dc.contributor.authorNooshabadi, Saeiden_US
dc.date.accessioned2020-12-18T09:23:55Z-
dc.date.available2020-12-18T09:23:55Z-
dc.date.issued2006en_US
dc.identifier.issn1546-1998en_US
dc.identifier.otherWoS-
dc.identifier.urihttp://hdl.handle.net/10553/76792-
dc.description.abstractThis paper presents the design of low power high performance arithmetic circuits using the feedthrough logic (FTL) 1 concept. FTL is ideally suited for the circuit design where the critical path is made of a large cascade of inverting gates. Its high fanout and high switching frequencies are due to both lower delay and dynamic power consumption. Low power FTL arithmetic circuits provides for smaller propagation delay time (2.6 times), lower energy consumption (31%), and similar combined delay, power consumption, and active area product, when compared with the standard CMOS technologies.en_US
dc.languageengen_US
dc.relation.ispartofJournal of Low Power Electronicsen_US
dc.sourceJournal of Low Power Electronics [ISSN 1546-1998], v. 2 (2), p. 300-307, 2006en_US
dc.subject2203 Electrónicaen_US
dc.subject.otherFeedthrough logicen_US
dc.subject.otherLow power arithmetic circuitsen_US
dc.subject.otherHigh speed CMOS techniquesen_US
dc.titleLow power and high performance arithmetic circuits in feedthrough CMOS logic family for low power applicationsen_US
dc.typeinfo:eu-repo/semantics/Articleen_US
dc.typeArticleen_US
dc.identifier.doi10.1166/jolpe.2006.066en_US
dc.identifier.isi000410174800016-
dc.identifier.eissn1546-2005-
dc.description.lastpage307en_US
dc.identifier.issue2-
dc.description.firstpage300en_US
dc.relation.volume8en_US
dc.investigacionCienciasen_US
dc.type2Artículoen_US
dc.contributor.daisngid5213989-
dc.contributor.daisngid480589-
dc.contributor.daisngid184255-
dc.description.numberofpages8en_US
dc.utils.revisionen_US
dc.contributor.wosstandardWOS:Navarro-Botello, V-
dc.contributor.wosstandardWOS:Montiel-Nelson, JA-
dc.contributor.wosstandardWOS:Nooshabadi, S-
dc.date.coverdateAgosto 2006en_US
dc.identifier.ulpgcen_US
dc.description.esciESCI
item.fulltextSin texto completo-
item.grantfulltextnone-
crisitem.author.deptGIR IUMA Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0003-4323-8097-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameNavarro Botello, Victor-
crisitem.author.fullNameMontiel Nelson, Juan Antonio-
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