Low power and high performance arithmetic circuits in feedthrough CMOS logic family for low power applications

Abstract

This paper presents the design of low power high performance arithmetic circuits using the feedthrough logic (FTL) 1 concept. FTL is ideally suited for the circuit design where the critical path is made of a large cascade of inverting gates. Its high fanout and high switching frequencies are due to both lower delay and dynamic power consumption. Low power FTL arithmetic circuits provides for smaller propagation delay time (2.6 times), lower energy consumption (31%), and similar combined delay, power consumption, and active area product, when compared with the standard CMOS technologies.