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López Feliciano, José Francisco

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Title Issue Date
Round-trip delay effect on iterative request-grant-accept scheduling algorithms for virtual output queue switches Tobajas, Félix ; Esper-Chaín Falcón, Roberto ; De Armas Sosa, Valentín ; López Feliciano, José Francisco ; Sarmiento Rodríguez, Roberto Issued date: 2002 DOI: 10.1109/GLOCOM.2002.1188528 Source: Globecom'02 [ISSN 1930-529X], v. 1-3, p. 1889-1893, (2002) Actas de congresos
VLSI video processing elements for real time applications López Feliciano, José Francisco ; Tobajas, F. ; López, S. ; Cortés, P.; Lalchand, S., et al Issued date: 2002 Source: IECON Proceedings (Industrial Electronics Conference),v. 3, p. 1930-1935 Actas de congresos
Low power, high speed, charge recycling CMOS threshold logic gate Celinski, P.; López Feliciano, José Francisco ; Al-Sarawi, S.; Abbott, D. Issued date: 2001 DOI: 10.1049/el:20010742 Source: Electronics Letters[ISSN 0013-5194],v. 37, p. 1067-1069 JCR: 0,97 - Q2 SCIE Artículo
A low power, high speed threshold logic and its application to the design of novel carry lookahead adders Celinski, Peter; López, Jose F. ; Al-Sarawi, S.; Abbott, Derek Issued date: 2001 DOI: 10.1117/12.449155 Source: Proceedings of SPIE - The International Society for Optical Engineering[ISSN 0277-786X],v. 4591, p. 258-265 Actas de congresos
A mapping technique for the synthesis of linear threshold gate networks used to implement Boolean functions Celinski, Peter; Sherman, Gregory D.; López, José Fco ; Abbott, Derek Issued date: 2001 Source: Advances in Neural Networks and Applications, p. 224-228 Reseña
Gallium arsenide processing elements for motion estimation full-search algorithm López Feliciano, José Francisco ; Cortés, P.; López, S. ; Sarmiento, R. Issued date: 2001 DOI: 10.1117/12.449139 Source: Proceedings of SPIE - The International Society for Optical Engineering[ISSN 0277-786X],v. 4591, p. 101-112 Actas de congresos
Gallium arsenide multiplierless filter bank for two dimensional discrete wavelet transform (2D-DWT) computation López Feliciano, José Francisco ; Lalchand Khemchandani, Sunil ; Tobajas, F. ; López, S. ; Núñez, A. , et al Issued date: 2001 DOI: 10.1117/12.449157 Source: Proceedings of SPIE - The International Society for Optical Engineering[ISSN 0277-786X],v. 4591, p. 273-280 Actas de congresos
Complementary neu-GaAs structure Celinski, P.; López, J. F. ; Al-Sarawi, S.; Abbott, D. Issued date: 2000 DOI: 10.1049/el:20000384 Source: Electronics Letters[ISSN 0013-5194],v. 36, p. 424-425 JCR: 0,931 - Q2 SCIE Artículo
Novel extension of neu-MOS techniques to neu-GaAs Celinski, P.; Abbott, D.; Al-Sarawi, S. F.; López Feliciano, José Francisco Issued date: 2000 Source: Microelectronics Journal[ISSN 0026-2692],v. 31, p. 577-582 JCR: 0,608 - Q2 SCIE Artículo
High-speed, low-power, asynchronous gallium arsenide systems for multimedia computing Lachowicz, S. W.; Eshraghian, K.; Lopez, J. F. ; Pfleiderer, H. J. Issued date: 1999 Source: Electron Technology (Warsaw)[ISSN 0070-9816],v. 32, p. 256-260 Artículo
Gallium arsenide technology for low-power, high performance processor cores Lachowicz, Stefan W.; Eshraghian, Kamran; Lopez, Jose F. Issued date: 1999 Source: Conference on Optoelectronic and Microelectronic Materials and Devices, Proceedings, COMMAD, p. 442-445 Artículo
Low power techniques for digital GaAs VLSI López Feliciano, José Francisco ; Sarmiento, R. ; Nunez, A. ; Eshraghian, K.; Lachowicz, S., et al Issued date: 1999 Source: Proceedings of the IEEE Great Lakes Symposium on VLSI[ISSN 1066-1395], p. 321-324 Actas de congresos
Neu-MOS (νMOS) for smart sensors and extension to a novel neu-GaAs (νGaAs) paradigm Abbott, D.; Al-Sarawi, S. F.; Gonzalez, B. ; Lopez, J. ; Austin-Crowe, J., et al Issued date: 1998 Source: Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems,v. 3, p. 397-404 Artículo
A CORDIC processor for FFT computation and its implementation using gallium arsenide technology Sarmiento, R ; Tobajas, Félix ; De Armas Sosa, Valentín ; Esper-Chaín, Roberto ; López Feliciano, José Francisco , et al Issued date: 1998 DOI: 10.1109/92.661241 Source: Ieee Transactions On Very Large Scale Integration (Vlsi) Systems[ISSN 1063-8210],v. 6 (1), p. 18-30 JCR: 0,733 - Q1 SCIE Artículo
Pipelined GaAs carry lookahead adder López Feliciano, José Francisco ; Reina, R.; Hernández, L.; Tobajas, F. ; De Armas Sosa, Valentín , et al Issued date: 1998 DOI: 10.1049/el:19981239 Source: Electronics Letters[ISSN 0013-5194],v. 34, p. 1732-1733 JCR: 1,152 - Q1 SCIE Artículo
Telecomunicaciones Sandoval González, Juan Domingo ; Núñez Ordóñez, Antonio ; López Feliciano, José Francisco ; Sarmiento Rodríguez, Roberto Issued date: 1998 Source: Gran Canaria siglo XXI: diagnóstico de situación / coord. por Francisco Javier Navarro de Tuero; Juan Manuel García Falcón (dir.), v. 1, (Tomo 1), p. 404-446 itemlist.container.dc.description.spiq Q4 Capítulo de libro
Investigación y desarrollo López Feliciano, José Francisco ; Sarmiento Rodríguez, Roberto ; Núñez Ordóñez, Antonio ; Sandoval González, Juan Domingo Issued date: 1998 Source: Gran Canaria siglo XXI: diagnóstico de situación / coord. por Francisco Javier Navarro de Tuero; Juan Manuel García Falcón (dir.), v. 2, (Tomo 2), p. 1467-1503 itemlist.container.dc.description.spiq Q4 Capítulo de libro
600 MHz 2D-DCT processor for MPEG applications Sarmiento, R. ; Pulido, C.; Tobajas, F. ; De Armas Sosa, Valentín ; Esper-Chain, R. , et al Issued date: 1998 Source: Conference Record of the Asilomar Conference on Signals, Systems and Computers[ISSN 1058-6393],v. 2, p. 1527-1531 Actas de congresos
Circuits for low power consumption in GaAs technology Reina, Rodrigo M.; Charry, Edgar R.; Lopez, José F. ; Sarmiento, R. Issued date: 1998 DOI: 10.1109/SBCCI.1998.715441 Source: Proceedings - 11th Brazilian Symposium on Integrated Circuit Design, SBCCI 1998,v. 1998-September (715441), p. 200-203 Actas de congresos
GaAs pseudodynamic latched logic for high performance processor cores López Feliciano, José Francisco ; Eshraghian, K.; Sarmiento, R. ; Núnez, A. ; Abbott, D. Issued date: 1997 DOI: 10.1109/4.604094 Source: IEEE Journal of Solid-State Circuits[ISSN 0018-9200],v. 32, p. 1297-1303 JCR: 0,922 - Q1 SCIE Artículo