Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/52228
Title: Low power, high speed, charge recycling CMOS threshold logic gate
Authors: Celinski, P.
López, J. F. 
Al-Sarawi, S.
Abbott, D.
Issue Date: 2001
Publisher: 0013-5194
Journal: Electronics letters 
Abstract: A new implementation of a threshold gate based on a capacitive input, charge recycling differential sense amplifier latch is presented. Simulation results indicate that the proposed structure has very low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations, and is therefore highly suitable as an element in digital integrated circuit design.
URI: http://hdl.handle.net/10553/52228
ISSN: 0013-5194
DOI: 10.1049/el:20010742
Source: Electronics Letters[ISSN 0013-5194],v. 37, p. 1067-1069
Appears in Collections:Artículos
Show full item record

SCOPUSTM   
Citations

41
checked on May 2, 2021

WEB OF SCIENCETM
Citations

34
checked on May 2, 2021

Page view(s)

13
checked on May 2, 2021

Google ScholarTM

Check

Altmetric


Share



Export metadata



Items in accedaCRIS are protected by copyright, with all rights reserved, unless otherwise indicated.