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Title: Low power, high speed, charge recycling CMOS threshold logic gate
Authors: Celinski, P.
López Feliciano, José Francisco 
Al-Sarawi, S.
Abbott, D.
Issue Date: 2001
Publisher: 0013-5194
Journal: Electronics letters 
Abstract: A new implementation of a threshold gate based on a capacitive input, charge recycling differential sense amplifier latch is presented. Simulation results indicate that the proposed structure has very low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations, and is therefore highly suitable as an element in digital integrated circuit design.
ISSN: 0013-5194
DOI: 10.1049/el:20010742
Source: Electronics Letters[ISSN 0013-5194],v. 37, p. 1067-1069
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