|Title:||600 MHz 2D-DCT processor for MPEG applications||Authors:||Sarmiento, R.
De Armas Sosa, Valentín
|UNESCO Clasification:||3307 Tecnología electrónica||Keywords:||Gallium arsenide
Discrete cosine transforms
Very large scale integration, et al
|Issue Date:||1998||Journal:||Conference Record of the Asilomar Conference on Signals, Systems and Computers||Conference:||31st Asilomar Conference on Signals, Systems and Computers
Proceedings of the 1997 31st Asilomar Conference on Signals, Systems & Computers. Part 1 (of 2)
|Abstract:||In this paper we present the design of a 2D discrete cosine transform (2D-DCT) processor and its implementation using 0.6 /spl mu/m GaAs technology. The architecture of the processor, that resembles an FCT-MMM (fast cosine transform-matrix matrix multiplication) architecture, was development using distributed arithmetic (DA) in order to reduce the area required. The processor has about 50k transistors and occupies an area of 31.8 mm/sup 2/. It is able to process 400 Mpixels per second and at a clock frequency of 600 MHz, which is far beyond the requirements for real time high definition moving pictures in the MPEG-2 standard. Special consideration is given to the implementation of a transposition RAM which constitutes the bottleneck of the algorithm. A 64 word/spl times/12 bit, 1 ns access time transposition RAM was developed using a new dynamic RAM cell.||URI:||http://hdl.handle.net/10553/45086||ISSN:||1058-6393||Source:||Conference Record of the Asilomar Conference on Signals, Systems and Computers[ISSN 1058-6393],v. 2, p. 1527-1531|
|Appears in Collections:||Actas de congresos|
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