Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/45085
Title: Circuits for low power consumption in GaAs technology
Authors: Reina, Rodrigo M.
Charry, Edgar R.
Lopez, José F. 
Sarmiento, R. 
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: Gallium arsenide
Power dissipation
Power supplies
Delay
MESFETs
Issue Date: 1998
Journal: Proceedings - 11th Brazilian Symposium on Integrated Circuit Design, SBCCI 1998
Conference: 11th Brazilian Symposium on Integrated Circuit Design, SBCCI 1998 
Abstract: In this paper we report the design of a new adder structure suitable for high speed, low power, digital applications. This adder was implemented using a new logic proposed recently, namely Pseudo-dynamic Latched Logic (PDDL), in MESFET technology using Vitesse H-GaAs III 0.6 /spl mu/m technology. Static and pseudo-dynamic adders were studied in order to make comparisons in terms of delay and power dissipation. These circuits were chosen due to the fact that they have a strong influence on the performance of data and signal processors. HSPICE simulation indicates operation up to 833 MHz with a 1 V power supply. Considering the delay-power characteristics as a function of power supply, it was found that a good tradeoff is obtained when using a 1 V power supply. Power dissipation of 4.96 /spl mu/W/MHz was obtained. Such extremely low power dissipation confirms that with this type of logic, high performance VLSI systems can be implemented.
URI: http://hdl.handle.net/10553/45085
ISBN: 0818687045
9780818687044
DOI: 10.1109/SBCCI.1998.715441
Source: Proceedings - 11th Brazilian Symposium on Integrated Circuit Design, SBCCI 1998,v. 1998-September (715441), p. 200-203
Appears in Collections:Actas de congresos
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