|Title:||Novel extension of neu-MOS techniques to neu-GaAs||Authors:||Celinski, P.
Al-Sarawi, S. F.
López, J. F.
|Keywords:||Complementary||Issue Date:||2000||Publisher:||0026-2692||Journal:||Microelectronics||Conference:||MICRO/MEMS 99 Symposium||Abstract:||The neuron-MOS (neu-MOS) transistor, recently discovered by Shibata and Ohmi in 1991 [T. Shibata, T. Ohmi, International Electron Devices Meeting, Technical Digest, 1991] uses capacitively coupled inputs onto a floating gate. Neu-MOS enables the design of conventional analog and digital integrated circuits with a significant reduction in transistor count [L.S.Y. Wong, C.Y. Kwok, G.A. Rigby, in: Proceedings of the 1997 IEEE Custom Integrated Circuits Conference, 1997; B. Gonzales, D. Abbott, S.F. Al-Sarawi, A. Hernandez, J. Garcia, J. Lopez, in: Proceedings of the XIII Design of Circuits and Integrated Systems Conference (DCIS'98), 1998, pp. 62-66]. Furthermore, neu-MOS circuit characteristics are relatively insensitive to transistor parameter variations inherent in all MOS fabrication processes. Neu-MOS circuit characteristics depend primarily on the floating gate coupling capacitor ratios. It is also thought that this enhancement in the functionality of the transistor, i.e. at the most elemental level in circuits, introduces a degree of flexibility that may lead to the realisation of intelligent functions at a system level [T. Ohmi, T. Shibata, in: Proceedings of the 20th International Conference on Microelectronics, vol. 1, 1995, pp. 11-18]. This paper extends the neu-MOS paradigm to complementary gallium arsenide based on HIGFET transistors. The design and HSPICE simulation results of a neu-GaAs ripple carry adder are presented, demonstrating the potential for very significant transistor count and area reduction through the use of neu-GaAs in VLSI design. Preliminary simulations indicate a reduction of a factor of four in transistor count for the same power dissipation as conventional complementary GaAs. The small gate leakage is shown to be useful in eliminating unwanted charge build-up on the floating gate. (C) 2000 Elsevier Science Ltd. All rights reserved.||URI:||http://hdl.handle.net/10553/52229||ISSN:||0026-2692||Source:||Microelectronics Journal[ISSN 0026-2692],v. 31, p. 577-582|
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