|Title:||Low power techniques for digital GaAs VLSI||Authors:||Lopez, J. F.
|UNESCO Clasification:||3307 Tecnología electrónica||Keywords:||Gallium arsenide
Very large scale integration
CMOS logic circuits
Silicon on insulator technology, et al
|Issue Date:||1999||Journal:||Proceedings of the IEEE Great Lakes Symposium on VLSI||Conference:||9th Great Lakes Symposium on VLSI (GLSVLSI 99)
Proceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99)
|Abstract:||This paper presents a survey of low-power digital Gallium Arsenide logic applicable to high performance VLSI circuits and systems and proposes new design concepts in methodology and architecture based on the implementation of Pseudo-Dynamic Latched Logic in order to achieve reasonable power-delay-area tradeoff. The approach is highly suitable for self-timed systems where the complexities of clock skew are avoided and power saving is achieved through pipelined architectures. The emergence of low-power Complementary HIGFET (C-HICFET) technology enables the realisation of new high performance low-power architectures. The viability of nu-GaAs (/spl nu/GaAs) as applied to C-HIGFET is discussed and the concept of 'soft' hardware referred as 'flexware' is introduced as a new design paradigm for GaAs.||URI:||http://hdl.handle.net/10553/45081||ISBN:||0769501044||ISSN:||1066-1395||Source:||Proceedings of the IEEE Great Lakes Symposium on VLSI[ISSN 1066-1395], p. 321-324|
|Appears in Collections:||Actas de congresos|
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