A mapping technique for the synthesis of linear threshold gate networks used to implement Boolean functions

Abstract

The main result of this paper is the development of a systematic paper-and-pencil design methodology for implementing Boolean functions of up to 4 variables using threshold logic (TL) gates, which does not require linear programming, for the first time. The methodology is similar in operation to the Karnaugh map logic minimization technique, and is based on determining the minimum threshold cover of a Boolean function. The paper also reviews aspects of TL and illustrates the application of the proposed design methodology to VLSI design using the neuron-MOS technique.