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López Feliciano, José Francisco

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50 artículo
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Title Issue Date
Gallium arsenide pseudo-dynamic latched logic López Feliciano, José ; Eshraghian, K.; Sarmiento, R. ; Núñez, A. Issued date: 1996 DOI: 10.1049/el:19960926 Source: Electronics Letters[ISSN 0013-5194],v. 32, p. 1353-1354 SCIE Artículo
Efficient design of gallium arsenide Muller-C element Eshraghian, K.; Lachowicz, S. W.; López Feliciano, José Francisco ; Sarmiento, R. Issued date: 1997 DOI: 10.1049/el:19970503 Source: Electronics Letters[ISSN 0013-5194],v. 33, p. 757-759 JCR: 1,005 - Q1 SCIE Artículo
GaAs pseudodynamic latched logic for high performance processor cores López Feliciano, José Francisco ; Eshraghian, K.; Sarmiento, R. ; Núnez, A. ; Abbott, D. Issued date: 1997 DOI: 10.1109/4.604094 Source: IEEE Journal of Solid-State Circuits[ISSN 0018-9200],v. 32, p. 1297-1303 JCR: 0,922 - Q1 SCIE Artículo
Noise margin enhancement in GaAs ROM's using current mode losic López Feliciano, José Francisco ; Sarmiento, R. ; Eshraghian, K.; Núñez, A. Issued date: 1997 DOI: 10.1109/4.563683 Source: IEEE Journal of Solid-State Circuits[ISSN 0018-9200],v. 32, p. 592-597 JCR: 0,922 - Q1 SCIE Artículo
A CORDIC processor for FFT computation and its implementation using gallium arsenide technology Sarmiento, R ; Tobajas, Félix ; De Armas Sosa, Valentín ; Esper-Chaín, Roberto ; López Feliciano, José Francisco , et al Issued date: 1998 DOI: 10.1109/92.661241 Source: Ieee Transactions On Very Large Scale Integration (Vlsi) Systems[ISSN 1063-8210],v. 6 (1), p. 18-30 JCR: 0,733 - Q1 SCIE Artículo
Pipelined GaAs carry lookahead adder López Feliciano, José Francisco ; Reina, R.; Hernández, L.; Tobajas, F. ; De Armas Sosa, Valentín , et al Issued date: 1998 DOI: 10.1049/el:19981239 Source: Electronics Letters[ISSN 0013-5194],v. 34, p. 1732-1733 JCR: 1,152 - Q1 SCIE Artículo
Neu-MOS (νMOS) for smart sensors and extension to a novel neu-GaAs (νGaAs) paradigm Abbott, D.; Al-Sarawi, S. F.; Gonzalez, B. ; Lopez, J. ; Austin-Crowe, J., et al Issued date: 1998 Source: Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems,v. 3, p. 397-404 Artículo
High-speed, low-power, asynchronous gallium arsenide systems for multimedia computing Lachowicz, S. W.; Eshraghian, K.; Lopez, J. F. ; Pfleiderer, H. J. Issued date: 1999 Source: Electron Technology (Warsaw)[ISSN 0070-9816],v. 32, p. 256-260 Artículo
Gallium arsenide technology for low-power, high performance processor cores Lachowicz, Stefan W.; Eshraghian, Kamran; Lopez, Jose F. Issued date: 1999 Source: Conference on Optoelectronic and Microelectronic Materials and Devices, Proceedings, COMMAD, p. 442-445 Artículo
Complementary neu-GaAs structure Celinski, P.; López, J. F. ; Al-Sarawi, S.; Abbott, D. Issued date: 2000 DOI: 10.1049/el:20000384 Source: Electronics Letters[ISSN 0013-5194],v. 36, p. 424-425 JCR: 0,931 - Q2 SCIE Artículo
Novel extension of neu-MOS techniques to neu-GaAs Celinski, P.; Abbott, D.; Al-Sarawi, S. F.; López Feliciano, José Francisco Issued date: 2000 Source: Microelectronics Journal[ISSN 0026-2692],v. 31, p. 577-582 JCR: 0,608 - Q2 SCIE Artículo
Low power, high speed, charge recycling CMOS threshold logic gate Celinski, P.; López Feliciano, José Francisco ; Al-Sarawi, S.; Abbott, D. Issued date: 2001 DOI: 10.1049/el:20010742 Source: Electronics Letters[ISSN 0013-5194],v. 37, p. 1067-1069 JCR: 0,97 - Q2 SCIE Artículo
A mapping technique for the synthesis of linear threshold gate networks used to implement Boolean functions Celinski, Peter; Sherman, Gregory D.; López, José Fco ; Abbott, Derek Issued date: 2001 Source: Advances in Neural Networks and Applications, p. 224-228 Reseña
Compact parallel (m,n) counters based on self-timed threshold logic Celinski, P.; López, J. F. ; Al-Sarawi, S.; Abbott, D. Issued date: 2002 DOI: 10.1049/el:20020438 Source: Electronics Letters[ISSN 0013-5194],v. 38, p. 633-635 SJR: 1,542 - Q1 SCIE Artículo
Adaptive motion vector post-processing for low cost rate-distortion optimisation López, S. ; Callicó, G. M. ; López Feliciano, José Francisco ; Sarmiento, R. Issued date: 2003 DOI: 10.1049/el:20031107 Source: Electronics Letters[ISSN 0013-5194],v. 39, p. 1720-1721 SJR: 1,278 - Q1 JCR: 1,01 - Q2 SCIE Artículo
Cell scheduling for VOQ switches with different strict priority levels Tobajas, F. ; Esper-Chaín, R. ; De Armas Sosa, Valentín ; López Feliciano, José Francisco ; Sarmiento, R. Issued date: 2003 DOI: 10.1049/el:20030334 Source: Electronics Letters[ISSN 0013-5194],v. 39, p. 580-581 SJR: 1,278 - Q1 JCR: 1,01 - Q2 SCIE Artículo
Cost-adaptive motion estimation strategy for high-performance video encoders López, S. ; López Feliciano, José Francisco ; Sarmiento, R. Issued date: 2005 DOI: 10.1049/el:20057045 Source: Electronics Letters[ISSN 0013-5194],v. 41, p. 182-183 SJR: 0,83 - Q1 JCR: 1,016 - Q2 SCIE Artículo
Compresión de vídeo mediante técnicas de post-procesamiento López Gustavo, Sebastián; Callicó, M.; López, J. Fco ; Sarmiento Rodríguez, Roberto Issued date: 2005 Source: Vector Plus. Las Palmas de Gran Canaria: Fundación Universitaria, 1994- ISSN 1134-5306, n.25, 2005 Artículo
Low-cost super-resolution algorithms implementation over a HW/SW video compression platform Callicó, Gustavo M. ; Llopis, Rafael Peset; López, Sebastian ; López Feliciano, José Francisco ; Núñez, Antonio , et al Issued date: 2006 DOI: 10.1155/ASP/2006/84614 Source: Eurasip Journal on Applied Signal Processing[ISSN 1110-8657],v. 2006 (84614) JCR: 0,463 - Q3 Artículo
Técnicas de súper-resolución para la mejora de secuencias de vídeo comprimido Marrero Callicó, Gustavo ; Barreto Dos Santos, Dácil; López Suárez, Sebastián ; Tarajano Beracoechea, Carlos; López Feliciano, José , et al Issued date: 2007 Source: Vector Plus. Las Palmas de Gran Canaria: Fundación Universitaria, 1994- ISSN 1134-5306, n.30, 2007, p. 34 Artículo