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Santana Jaria, Oliverio Jesús

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El Proyecto Excerpta y el mar Arcos Pereira, Trinidad ; Cuyás de Torres, Mª Elisa ; Domínguez Rodríguez, María Victoria ; García de Paso Carrasco, María Dolores ; Rodríguez Álvarez, Alicia , et al Issued date: 2019 Póster de congresos
Author retrospective for Software trace cache Ramirez, Alex; Falcón, Ayose J.; Santana, Oliverio J. ; Valero, Mateo Issued date: 2014 DOI: 10.1145/2591635.2594508 Source: Proceedings of the International Conference on Supercomputing, p. 45-47 Actas de congresos
Efficient runahead threads Ramirez, Tanausú; Pajuelo, Alex; Santana, Oliverio Jesus ; Mutlu, Onur; Valero, Mateo Issued date: 2010 DOI: 10.1145/1854273.1854328 Source: Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT[ISSN 1089-795X],v. 2010, p. 443-452 Actas de congresos
On the problem of evaluating the performance of multiprogrammed workloads Cazorla, Francisco J.; Pajuelo, Alex; Santana, Oliverio J. ; Fernandez, Enrique; Valero, Mateo Issued date: 2010 DOI: 10.1109/TC.2010.62 Source: IEEE Transactions on Computers[ISSN 0018-9340],v. 59 (5432159), p. 1722-1728 JCR: 1,608 - Q1 SCIE Artículo
DIA: a complexity-effective decoding architecture Santana, Oliverio J. ; Falcón, Ayose; Ramirez, Alex; Valero, Mateo Issued date: 2009 DOI: 10.1109/TC.2008.170 Source: IEEE Transactions on Computers [ISSN 0018-9340], v. 58, p. 448-462 JCR: 1,822 - Q1 SCIE Artículo
Code semantic-aware runahead threads Ramírez, Tanauśu; Pajuelo, Alex; Santana, Oliverio J. ; Valero, Mateo Issued date: 2009 DOI: 10.1109/ICPP.2009.17 Source: Proceedings of the International Conference on Parallel Processing[ISSN 0190-3918] (5362436), p. 437-444 Actas de congresos
LPA: a first approach to the loop processor architecture García, Alejandro; Santana Jaria, Oliverio Jesús ; Fernández García, Enrique ; Medina Rodríguez, Pedro ; Valero, Mateo Issued date: 2008 DOI: 10.1007/978-3-540-77560-7_19 Source: Stenström P., Dubois M., Katevenis M., Gupta R., Ungerer T. (eds) High Performance Embedded Architectures and Compilers. HiPEAC 2008. Lecture Notes in Computer Science, vol 4917. Springer, Berlin, Heidelberg Actas de congresos
Multiple stream prediction Santana, Oliverio J. ; Ramirez, Alex; Valero, Mateo Issued date: 2008 Source: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)[ISSN 0302-9743],v. 4759 LNCS, p. 1-16 Actas de congresos
Runahead threads to improve SMT performance Ramírez, Tanausú; Pajuelo, Alex; Santana, Oliverio J. ; Valero, Mateo Issued date: 2008 DOI: 10.1109/HPCA.2008.4658635 Source: 2008 Ieee 14Th International Symposium On High Peformance Computer Architecture [ISSN 1530-0897], p. 149-158, (2008) Actas de congresos
FAME: FAirly MEasuring multithreaded architectures Vera, Javier; Cazorla, Francisco J.; Pajuelo, Alex; Santana, Oliverio J. ; Fernández, Enrique , et al Issued date: 2007 DOI: 10.1109/PACT.2007.4336221 Source: Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT [ISSN 1089-795X], n. 4336221, p. 305-316 Actas de congresos
Measuring the performance of multithreaded processors Vera, Javier; Cazorla, Francisco J.; Pajuelo, Alex; Santana, Oliverio J. ; Fernandez, Enrique , et al Issued date: 2007 Source: 2007 SPEC Benchmark Workshop Actas de congresos
Enlarging instruction streams Santana, Oliverio J. ; Ramirez, Alex; Valero, Mateo Issued date: 2007 DOI: 10.1109/TC.2007.70742 Source: IEEE Transactions on Computers[ISSN 0018-9340],v. 56, p. 1342-1357 JCR: 1,68 - Q1 SCIE Artículo
Runahead threads: reducing resource contention in SMT processors Ramírez, Tanausú; Pajuelo, Alex; Santana, Oliverio J. ; Valero, Mateo Issued date: 2007 Source: Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT[ISSN 1089-795X] (4336251), p. 423 Actas de congresos
Branch predictor guided instruction decoding Santana, Oliverio J. ; Falcón, Ayose; Ramirez, Alex; Valero, Mateo Issued date: 2006 DOI: 10.1145/1152154.1152186 Source: Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT[ISSN 1089-795X],v. 2006, p. 202-211 Actas de congresos
A simple speculative load control mechanism for energy saving Ramírez, Tanaus; Pajuelo, Alex; Santana, Oliverio J. ; Valero, Mateo Issued date: 2006 DOI: 10.1145/1166133.1166137 Source: Proceedings of the 2006 Workshop on MEmory Performance: DEaling with Applications, Systems and Architectures, MEDEA '06,v. 2006, p. 29-36 Actas de congresos
Kilo-instruction processors, runahead and prefetching Ramírez, Tanausú; Pajuelo González, Alejandro; Santana, Oliverio J. ; Valero Cortés, Mateo Issued date: 2006 DOI: 10.1145/1128022.1128059 Source: Proceedings of the 3rd Conference on Computing Frontiers 2006, CF '06, [ISSN 2687-9247], 2006, p. 269-278, (Diciembre 2006) Actas de congresos
Kilo-instruction processors: overcoming the memory wall Cristal, Adrián; Santana, Oliverio J. ; Cazorla, Francisco; Galluzzi, Marco; Ramírez, Tanausú, et al Issued date: 2005 DOI: 10.1109/MM.2005.53 Source: IEEE Micro [ISSN 0272-1732], v. 25 (3), p. 48-57 JCR: 1,238 - Q2 SCIE Artículo
Maintaining thousands of in-flight instructions Cristal, Adrian; Santana, Oliverio J. ; Valero, Mateo Issued date: 2004 DOI: 10.1007/978-3-540-27866-5_2 Source: Danelutto M., Vanneschi M., Laforenza D. (eds) Euro-Par 2004 Parallel Processing. Euro-Par 2004. Lecture Notes in Computer Science, vol 3149. Springer, Berlin, Heidelberg JCR: 0,513 - Q4 Actas de congresos
Reducing fetch architecture complexity using procedure inlining Santana, Oliverio J. ; Ramirez, Alex; Valero, Mateo Issued date: 2004 DOI: 10.1109/INTERA.2004.1299514 Source: Proceedings - Eighth Workshop on Interaction between Compilers and Computer Architectures, INTERACT-8 2004, p. 97-106 Actas de congresos
Toward kilo-instruction processors Cristal, Adrián; Santana, Oliverio J. ; Valero, Mateo; Martínez, José F. Issued date: 2004 DOI: 10.1145/1044823.1044825 Source: ACM Transactions on Architecture and Code Optimization [ISSN 1544-3566], v. 1 (4), p. 389-417 SCIE Artículo