|Title:||A simple speculative load control mechanism for energy saving||Authors:||Ramírez, Tanaus
Santana, Oliverio J.
|UNESCO Clasification:||330406 Arquitectura de ordenadores||Issue Date:||2006||Journal:||Proceedings of the 2006 Workshop on MEmory Performance: DEaling with Applications, Systems and Architectures, MEDEA '06||Conference:||2006 Workshop on MEmory Performance: DEaling with Applications, Systems and Architectures, MEDEA '06||Abstract:||To alleviate the memory wall problem, current architectural trends suggest implementing large instruction windows able to maintain a high number of in-flight instructions. However, the benefits achieved by these recent proposals may be limited because more instructions are executed down the wrong path of a mispredicted branch, likely polluting the processor caches. The larger number of misspeculated instructions involves increasing the energy consumed compared to traditional designs with smaller instruction windows. Our analysis shows that, for some SPEC2000 integer benchmarks, up to 2,5X wrong-path load instructions are executed when the instruction window of a 4-way superscalar processor is increased from 256 to 1024 entries.This paper describes a simple speculative control technique to prevent wrong-path load instructions from being executed. Our technique extends the functionality of the load-store queue to block those load instructions that depend on a hard-to-predict conditional branch until it is resolved. If the branch is actually mispredicted, unnecessary cache misses can be avoided, saving energy down the wrong path. Furthermore, instructions that depend on a blocked load are not issued because their source values are not available, which also saves energy. Our results show that the proposed mechanism reduces, on average, up to 26% misspeculated load instructions and 18% wrong-path instructions without any performance loss.||URI:||http://hdl.handle.net/10553/50499||ISBN:||1595935681
|DOI:||10.1145/1166133.1166137||Source:||Proceedings of the 2006 Workshop on MEmory Performance: DEaling with Applications, Systems and Architectures, MEDEA '06,v. 2006, p. 29-36|
|Appears in Collections:||Actas de congresos|
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