Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/50497
Title: Enlarging instruction streams
Authors: Santana, Oliverio J. 
Ramirez, Alex
Valero, Mateo
UNESCO Clasification: 330406 Arquitectura de ordenadores
Issue Date: 2007
Publisher: 0018-9340
Journal: IEEE Transactions on Computers 
Abstract: The stream fetch engine is a high-performance fetch architecture based on the concept of an instruction stream. We call a sequence of instructions from the target of a taken branch to the next taken branch, potentially containing multiple basic blocks, a stream. The long length of instruction streams makes it possible for the stream fetch engine to provide a high fetch bandwidth and to hide the branch predictor access latency, leading to performance results close to a trace cache at a lower implementation cost and complexity. Therefore, enlarging instruction streams is an excellent way to improve the stream fetch engine. In this paper, we present several hardware and software mechanisms focused on enlarging those streams that finalize at particular branch types. However, our results point out that focusing on particular branch types is not a good strategy due to Amdahl's law. Consequently, we propose the multiple-stream predictor, a novel mechanism that deals with all branch types by combining single streams into long virtual streams. This proposal tolerates the prediction table access latency without requiring the complexity caused by additional hardware mechanisms like prediction overriding. Moreover, it provides high-performance results which are comparable to state-of-the-art fetch architectures but with a simpler design that consumes less energy.
URI: http://hdl.handle.net/10553/50497
ISSN: 0018-9340
DOI: 10.1109/TC.2007.70742
Source: IEEE Transactions on Computers[ISSN 0018-9340],v. 56, p. 1342-1357
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