|Title:||LPA: a first approach to the loop processor architecture||Authors:||García, Alejandro
Santana, Oliverio J.
|UNESCO Clasification:||330406 Arquitectura de ordenadores||Keywords:||Loop iteration
|Issue Date:||2008||Journal:||Lecture Notes in Computer Science||Conference:||3rd International Conference on High Performance Embedded Architectures and Compilers
3rd International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2008
|Abstract:||Current processors frequently run applications containing loop structures. However, traditional processor designs do not take into account the semantic information of the executed loops, failing to exploit an important opportunity. In this paper, we take our first step toward a loop-conscious processor architecture that has great potential to achieve high performance and relatively low energy consumption. In particular, we propose to store simple dynamic loops in a buffer, namely the loop window. Loop instructions are kept in the loop window along with all the information needed to build the rename mapping. Therefore, the loop window can directly feed the execution back-end queues with instructions, avoiding the need for using the prediction, fetch, decode, and rename stages of the normal processor pipeline. Our results show that the loop window is a worthwhile complexity-effective alternative for processor design that reduces front-end activity by 14% for SPECint benchmarks and by 45% for SPECfp benchmarks.||URI:||http://hdl.handle.net/10553/43887||ISBN:||978-3-540-77559-1||ISSN:||0302-9743||DOI:||10.1007/978-3-540-77560-7_19||Source:||Stenström P., Dubois M., Katevenis M., Gupta R., Ungerer T. (eds) High Performance Embedded Architectures and Compilers. HiPEAC 2008. Lecture Notes in Computer Science, vol 4917. Springer, Berlin, Heidelberg|
|Appears in Collections:||Actas de congresos|
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