Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/43887
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dc.contributor.authorGarcía, Alejandroen_US
dc.contributor.authorSantana Jaria, Oliverio Jesúsen_US
dc.contributor.authorFernández García, Enriqueen_US
dc.contributor.authorMedina Rodríguez, Pedroen_US
dc.contributor.authorValero, Mateoen_US
dc.date.accessioned2018-11-21T18:37:07Z-
dc.date.available2018-11-21T18:37:07Z-
dc.date.issued2008en_US
dc.identifier.isbn978-3-540-77559-1en_US
dc.identifier.issn0302-9743en_US
dc.identifier.urihttp://hdl.handle.net/10553/43887-
dc.description.abstractCurrent processors frequently run applications containing loop structures. However, traditional processor designs do not take into account the semantic information of the executed loops, failing to exploit an important opportunity. In this paper, we take our first step toward a loop-conscious processor architecture that has great potential to achieve high performance and relatively low energy consumption. In particular, we propose to store simple dynamic loops in a buffer, namely the loop window. Loop instructions are kept in the loop window along with all the information needed to build the rename mapping. Therefore, the loop window can directly feed the execution back-end queues with instructions, avoiding the need for using the prediction, fetch, decode, and rename stages of the normal processor pipeline. Our results show that the loop window is a worthwhile complexity-effective alternative for processor design that reduces front-end activity by 14% for SPECint benchmarks and by 45% for SPECfp benchmarks.-
dc.languageengen_US
dc.publisherSpringeren_US
dc.relation.ispartofLecture Notes in Computer Scienceen_US
dc.sourceStenström P., Dubois M., Katevenis M., Gupta R., Ungerer T. (eds) High Performance Embedded Architectures and Compilers. HiPEAC 2008. Lecture Notes in Computer Science, vol 4917. Springer, Berlin, Heidelbergen_US
dc.subject330406 Arquitectura de ordenadores-
dc.subject.otherLoop iteration-
dc.subject.otherLoop body-
dc.subject.otherLogical register-
dc.subject.otherPerformance speedup-
dc.subject.otherInstruction cache-
dc.titleLPA: a first approach to the loop processor architectureen_US
dc.typeinfo:eu-repo/semantics/conferenceObjecten_US
dc.typeConferenceObjecten_US
dc.relation.conference3rd International Conference on High Performance Embedded Architectures and Compilersen_US
dc.identifier.doi10.1007/978-3-540-77560-7_19en_US
dc.identifier.scopus49949105678-
dc.identifier.isi000252961400018-
dc.contributor.orcid#NODATA#-
dc.contributor.orcid#NODATA#-
dc.contributor.orcid#NODATA#-
dc.contributor.orcid#NODATA#-
dc.contributor.orcid#NODATA#-
dc.contributor.authorscopusid55452188800-
dc.contributor.authorscopusid7003605046-
dc.contributor.authorscopusid36476145100-
dc.contributor.authorscopusid24605829000-
dc.contributor.authorscopusid24475914200-
dc.identifier.eissn1611-3349-
dc.description.lastpage287en_US
dc.description.firstpage273en_US
dc.relation.volume4917en_US
dc.investigacionIngeniería y Arquitectura-
dc.type2Actas de congresosen_US
dc.contributor.daisngid31376846-
dc.contributor.daisngid3401331-
dc.contributor.daisngid30617825-
dc.contributor.daisngid5558543-
dc.contributor.daisngid41870-
dc.identifier.eisbn978-3-540-77560-7-
dc.utils.revision-
dc.contributor.wosstandardWOS:Garcia, A-
dc.contributor.wosstandardWOS:Santana, OJ-
dc.contributor.wosstandardWOS:Fernandez, E-
dc.contributor.wosstandardWOS:Medina, P-
dc.contributor.wosstandardWOS:Valero, M-
dc.date.coverdateAgosto 2008en_US
dc.identifier.conferenceidevents120604-
dc.identifier.conferenceidevents121349-
dc.identifier.ulpgc-
dc.contributor.buulpgcBU-TELen_US
item.grantfulltextopen-
item.fulltextCon texto completo-
crisitem.event.eventsstartdate27-01-2008-
crisitem.event.eventsenddate29-01-2008-
crisitem.author.deptGIR SIANI: Inteligencia Artificial, Robótica y Oceanografía Computacional-
crisitem.author.deptIU Sistemas Inteligentes y Aplicaciones Numéricas-
crisitem.author.deptDepartamento de Informática y Sistemas-
crisitem.author.deptDepartamento de Informática y Sistemas-
crisitem.author.deptDepartamento de Informática y Sistemas-
crisitem.author.orcid0000-0001-7511-5783-
crisitem.author.orcidhttps://orcid.org/0000-0001-9099-2573-
crisitem.author.parentorgIU Sistemas Inteligentes y Aplicaciones Numéricas-
crisitem.author.fullNameSantana Jaria, Oliverio Jesús-
crisitem.author.fullNameFernández García, Enrique-
crisitem.author.fullNameMedina Rodríguez, Pedro-
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