Please use this identifier to cite or link to this item:
http://hdl.handle.net/10553/43887
DC Field | Value | Language |
---|---|---|
dc.contributor.author | García, Alejandro | en_US |
dc.contributor.author | Santana Jaria, Oliverio Jesús | en_US |
dc.contributor.author | Fernández García, Enrique | en_US |
dc.contributor.author | Medina Rodríguez, Pedro | en_US |
dc.contributor.author | Valero, Mateo | en_US |
dc.date.accessioned | 2018-11-21T18:37:07Z | - |
dc.date.available | 2018-11-21T18:37:07Z | - |
dc.date.issued | 2008 | en_US |
dc.identifier.isbn | 978-3-540-77559-1 | en_US |
dc.identifier.issn | 0302-9743 | en_US |
dc.identifier.uri | http://hdl.handle.net/10553/43887 | - |
dc.description.abstract | Current processors frequently run applications containing loop structures. However, traditional processor designs do not take into account the semantic information of the executed loops, failing to exploit an important opportunity. In this paper, we take our first step toward a loop-conscious processor architecture that has great potential to achieve high performance and relatively low energy consumption. In particular, we propose to store simple dynamic loops in a buffer, namely the loop window. Loop instructions are kept in the loop window along with all the information needed to build the rename mapping. Therefore, the loop window can directly feed the execution back-end queues with instructions, avoiding the need for using the prediction, fetch, decode, and rename stages of the normal processor pipeline. Our results show that the loop window is a worthwhile complexity-effective alternative for processor design that reduces front-end activity by 14% for SPECint benchmarks and by 45% for SPECfp benchmarks. | - |
dc.language | eng | en_US |
dc.publisher | Springer | en_US |
dc.relation.ispartof | Lecture Notes in Computer Science | en_US |
dc.source | Stenström P., Dubois M., Katevenis M., Gupta R., Ungerer T. (eds) High Performance Embedded Architectures and Compilers. HiPEAC 2008. Lecture Notes in Computer Science, vol 4917. Springer, Berlin, Heidelberg | en_US |
dc.subject | 330406 Arquitectura de ordenadores | - |
dc.subject.other | Loop iteration | - |
dc.subject.other | Loop body | - |
dc.subject.other | Logical register | - |
dc.subject.other | Performance speedup | - |
dc.subject.other | Instruction cache | - |
dc.title | LPA: a first approach to the loop processor architecture | en_US |
dc.type | info:eu-repo/semantics/conferenceObject | en_US |
dc.type | ConferenceObject | en_US |
dc.relation.conference | 3rd International Conference on High Performance Embedded Architectures and Compilers | en_US |
dc.identifier.doi | 10.1007/978-3-540-77560-7_19 | en_US |
dc.identifier.scopus | 49949105678 | - |
dc.identifier.isi | 000252961400018 | - |
dc.contributor.orcid | #NODATA# | - |
dc.contributor.orcid | #NODATA# | - |
dc.contributor.orcid | #NODATA# | - |
dc.contributor.orcid | #NODATA# | - |
dc.contributor.orcid | #NODATA# | - |
dc.contributor.authorscopusid | 55452188800 | - |
dc.contributor.authorscopusid | 7003605046 | - |
dc.contributor.authorscopusid | 36476145100 | - |
dc.contributor.authorscopusid | 24605829000 | - |
dc.contributor.authorscopusid | 24475914200 | - |
dc.identifier.eissn | 1611-3349 | - |
dc.description.lastpage | 287 | en_US |
dc.description.firstpage | 273 | en_US |
dc.relation.volume | 4917 | en_US |
dc.investigacion | Ingeniería y Arquitectura | - |
dc.type2 | Actas de congresos | en_US |
dc.contributor.daisngid | 31376846 | - |
dc.contributor.daisngid | 3401331 | - |
dc.contributor.daisngid | 30617825 | - |
dc.contributor.daisngid | 5558543 | - |
dc.contributor.daisngid | 41870 | - |
dc.identifier.eisbn | 978-3-540-77560-7 | - |
dc.utils.revision | Sí | - |
dc.contributor.wosstandard | WOS:Garcia, A | - |
dc.contributor.wosstandard | WOS:Santana, OJ | - |
dc.contributor.wosstandard | WOS:Fernandez, E | - |
dc.contributor.wosstandard | WOS:Medina, P | - |
dc.contributor.wosstandard | WOS:Valero, M | - |
dc.date.coverdate | Agosto 2008 | en_US |
dc.identifier.conferenceid | events120604 | - |
dc.identifier.conferenceid | events121349 | - |
dc.identifier.ulpgc | Sí | - |
dc.contributor.buulpgc | BU-TEL | en_US |
item.fulltext | Con texto completo | - |
item.grantfulltext | open | - |
crisitem.event.eventsstartdate | 27-01-2008 | - |
crisitem.event.eventsenddate | 29-01-2008 | - |
crisitem.author.dept | GIR SIANI: Inteligencia Artificial, Robótica y Oceanografía Computacional | - |
crisitem.author.dept | IU Sistemas Inteligentes y Aplicaciones Numéricas | - |
crisitem.author.dept | Departamento de Informática y Sistemas | - |
crisitem.author.dept | Departamento de Informática y Sistemas | - |
crisitem.author.dept | Departamento de Informática y Sistemas | - |
crisitem.author.orcid | 0000-0001-7511-5783 | - |
crisitem.author.orcid | https://orcid.org/0000-0001-9099-2573 | - |
crisitem.author.parentorg | IU Sistemas Inteligentes y Aplicaciones Numéricas | - |
crisitem.author.fullName | Santana Jaria, Oliverio Jesús | - |
crisitem.author.fullName | Fernández García, Enrique | - |
crisitem.author.fullName | Medina Rodríguez, Pedro | - |
Appears in Collections: | Actas de congresos |
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