Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/50500
Title: Kilo-instruction processors: overcoming the memory wall
Authors: Cristal, Adrián
Santana, Oliverio J. 
Cazorla, Francisco
Galluzzi, Marco
Ramírez, Tanausú
Pericàs, Miquel
Valero, Mateo
UNESCO Clasification: 330406 Arquitectura de ordenadores
Keywords: Kilo-instruction processors
Superscalar processors
In-flight instructions
Memory wall
ROB, et al
Issue Date: 2005
Journal: IEEE Micro 
Abstract: Historically, advances in integrated circuit technology have driven improvements in processor microarchitecture and led to todays microprocessors with sophisticated pipelines operating at very high clock frequencies. However, performance improvements achievable by high-frequency microprocessors have become seriously limited by main-memory access latencies because main-memory speeds have improved at a much slower pace than microprocessor speeds. Its crucial to deal with this performance disparity, commonly known as the memory wall, to enable future high-frequency microprocessors to achieve their performance potential. To overcome the memory wall, we propose kilo-instruction processors-superscalar processors that can maintain a thousand or more simultaneous in-flight instructions. Doing so means designing key hardware structures so that the processor can satisfy the high resource requirements without significantly decreasing processor efficiency or increasing energy consumption.
URI: http://hdl.handle.net/10553/50500
ISSN: 0272-1732
DOI: 10.1109/MM.2005.53
Source: IEEE Micro [ISSN 0272-1732], v. 25 (3), p. 48-57
Appears in Collections:Artículos
Show full item record

SCOPUSTM   
Citations

36
checked on May 2, 2021

WEB OF SCIENCETM
Citations

18
checked on May 2, 2021

Page view(s)

33
checked on May 3, 2021

Google ScholarTM

Check

Altmetric


Share



Export metadata



Items in accedaCRIS are protected by copyright, with all rights reserved, unless otherwise indicated.