Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/50500
DC FieldValueLanguage
dc.contributor.authorCristal, Adriánen_US
dc.contributor.authorSantana, Oliverio J.en_US
dc.contributor.authorCazorla, Franciscoen_US
dc.contributor.authorGalluzzi, Marcoen_US
dc.contributor.authorRamírez, Tanausúen_US
dc.contributor.authorPericàs, Miquelen_US
dc.contributor.authorValero, Mateoen_US
dc.date.accessioned2018-11-24T16:31:18Z-
dc.date.available2018-11-24T16:31:18Z-
dc.date.issued2005en_US
dc.identifier.issn0272-1732en_US
dc.identifier.urihttp://hdl.handle.net/10553/50500-
dc.description.abstractHistorically, advances in integrated circuit technology have driven improvements in processor microarchitecture and led to todays microprocessors with sophisticated pipelines operating at very high clock frequencies. However, performance improvements achievable by high-frequency microprocessors have become seriously limited by main-memory access latencies because main-memory speeds have improved at a much slower pace than microprocessor speeds. Its crucial to deal with this performance disparity, commonly known as the memory wall, to enable future high-frequency microprocessors to achieve their performance potential. To overcome the memory wall, we propose kilo-instruction processors-superscalar processors that can maintain a thousand or more simultaneous in-flight instructions. Doing so means designing key hardware structures so that the processor can satisfy the high resource requirements without significantly decreasing processor efficiency or increasing energy consumption.en_US
dc.languageengen_US
dc.relation.ispartofIEEE Microen_US
dc.sourceIEEE Micro [ISSN 0272-1732], v. 25 (3), p. 48-57en_US
dc.subject330406 Arquitectura de ordenadoresen_US
dc.subject.otherKilo-instruction processorsen_US
dc.subject.otherSuperscalar processorsen_US
dc.subject.otherIn-flight instructionsen_US
dc.subject.otherMemory wallen_US
dc.subject.otherROBen_US
dc.subject.otherIssue queueen_US
dc.titleKilo-instruction processors: overcoming the memory wallen_US
dc.typeinfo:eu-repo/semantics/articlees
dc.typeArticlees
dc.identifier.doi10.1109/MM.2005.53en_US
dc.identifier.scopus22944446075-
dc.identifier.isi000229934100006-
dc.contributor.authorscopusid55884958300-
dc.contributor.authorscopusid7003605046-
dc.contributor.authorscopusid55129883300-
dc.contributor.authorscopusid8537030700-
dc.contributor.authorscopusid35608297100-
dc.contributor.authorscopusid35743631600-
dc.contributor.authorscopusid24475914200-
dc.identifier.eissn1937-4143-
dc.description.lastpage57-
dc.identifier.issue3-
dc.description.firstpage48-
dc.relation.volume25-
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Artículoen_US
dc.utils.revisionen_US
dc.identifier.ulpgces
dc.description.jcr1,238
dc.description.jcrqQ2
dc.description.scieSCIE
item.grantfulltextnone-
item.fulltextSin texto completo-
crisitem.author.deptGIR SIANI: Inteligencia Artificial, Robótica y Oceanografía Computacional-
crisitem.author.deptIU Sistemas Inteligentes y Aplicaciones Numéricas-
crisitem.author.deptDepartamento de Informática y Sistemas-
crisitem.author.orcid0000-0001-7511-5783-
crisitem.author.parentorgIU Sistemas Inteligentes y Aplicaciones Numéricas-
crisitem.author.fullNameSantana Jaria, Oliverio Jesús-
Appears in Collections:Artículos
Show simple item record

SCOPUSTM   
Citations

38
checked on Jun 19, 2022

WEB OF SCIENCETM
Citations

20
checked on Jun 19, 2022

Page view(s)

39
checked on Mar 13, 2022

Google ScholarTM

Check

Altmetric


Share



Export metadata



Items in accedaCRIS are protected by copyright, with all rights reserved, unless otherwise indicated.