Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/42183
Title: Area efficient dual-fed CMOS distributed power amplifier
Authors: del Pino, Javier 
Khemchandani, Sunil L. 
Mateos-Angulo, Sergio
Mayor-Duarte, Daniel
San-Miguel-Montesdeoca, Mario
Keywords: 330790 Microelectrónica
metadata.dc.subject.other: Distributed power amplifier
Dual-fed
Stacked inductor
Multilevel inductor
Area reduction
Issue Date: 2018
Journal: Electronics (Switzerland) 
Abstract: In this paper, an area-efficient 4-stage dual-fed distributed power amplifier (DPA) implemented in a 0.35 µm Complementary Metal Oxide Semiconductor (CMOS) process is presented. To effectively reduce the area of the circuit, techniques such as using multilevel inductors and closely-placing conventional spiral inductors are employed. Additionally, a novel technique based on stacking inductors one on top of others is implemented. Based on these techniques, a 32% area reduction is achieved compared to a conventional design without a noticeable performance degradation. This reduction could be further exploited as the number of stages of the dual-fed DPA increases.
URI: http://hdl.handle.net/10553/42183
ISSN: 2079-9292
DOI: 10.3390/electronics7080139
Source: Electronics (Switzerland),v. 7 (139)
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