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http://hdl.handle.net/10553/42183
Title: | Area efficient dual-fed CMOS distributed power amplifier | Authors: | del Pino, Javier Khemchandani, Sunil L. Mateos Angulo, Sergio Mayor Duarte, Daniel San Miguel Montesdeoca, Mario |
UNESCO Clasification: | 330790 Microelectrónica | Keywords: | Distributed power amplifier Dual-fed Stacked inductor Multilevel inductor Area reduction |
Issue Date: | 2018 | Project: | TEC2015-71072-C03-01 Diseño de Amplificadores de Potencia Integrados de Nitruro de Galio Para Comunicaciones |
Journal: | Electronics (Switzerland) | Abstract: | In this paper, an area-efficient 4-stage dual-fed distributed power amplifier (DPA) implemented in a 0.35 µm Complementary Metal Oxide Semiconductor (CMOS) process is presented. To effectively reduce the area of the circuit, techniques such as using multilevel inductors and closely-placing conventional spiral inductors are employed. Additionally, a novel technique based on stacking inductors one on top of others is implemented. Based on these techniques, a 32% area reduction is achieved compared to a conventional design without a noticeable performance degradation. This reduction could be further exploited as the number of stages of the dual-fed DPA increases. | URI: | http://hdl.handle.net/10553/42183 | ISSN: | 2079-9292 | DOI: | 10.3390/electronics7080139 | Source: | Electronics (Switzerland) [ISSN 2079-9292], v. 7 (139) |
Appears in Collections: | Artículos |
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