Identificador persistente para citar o vincular este elemento:
http://hdl.handle.net/10553/49665
| Título: | Design of energy efficient 10ps per bit adder circuits in CMOS | Autores/as: | Navarro Botello, Victor Montiel-Nelson, Juan A. Nooshabadi, Saeid |
Clasificación UNESCO: | 3307 Tecnología electrónica | Palabras clave: | Energy efficiency Adders CMOS logic circuits MOS devices Semiconductor device measurement, et al. |
Fecha de publicación: | 2008 | Publicación seriada: | Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 | Conferencia: | 4th IEEE Asian Solid-State Circuits Conference | Resumen: | This work presents the experimental results, from chip measurements, of ripple carry adder circuits using a new CMOS logic family -Feedthrough Logic (FTL). A 14-bit low power FTL adder performs faster, (2.6 times smaller propagation time delay, and 1.85 times higher maximum frequency), and provides a better energy efficiency (67.9% saving), when compared with the dynamic domino CMOS logic style. The 18-bit high speed FTL, working at its maximum frequency, outperforms the dynamic domino logic in terms of the propagation delay (19.5 times less), maximum frequency (12.1 times more), and energy efficiency per bit (96.7% better). | URI: | http://hdl.handle.net/10553/49665 | ISBN: | 9781424426058 | DOI: | 10.1109/ASSCC.2008.4708735 | Fuente: | Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 (4708735), p. 85-88 |
| Colección: | Actas de congresos |
Los elementos en ULPGC accedaCRIS están protegidos por derechos de autor con todos los derechos reservados, a menos que se indique lo contrario.