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Title: Design of energy efficient 10ps per bit adder circuits in CMOS
Authors: Navarro Botello, Victor 
Montiel-Nelson, Juan A. 
Nooshabadi, Saeid
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: Energy efficiency
CMOS logic circuits
MOS devices
Semiconductor device measurement, et al
Issue Date: 2008
Journal: Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Conference: 4th IEEE Asian Solid-State Circuits Conference 
Abstract: This work presents the experimental results, from chip measurements, of ripple carry adder circuits using a new CMOS logic family -Feedthrough Logic (FTL). A 14-bit low power FTL adder performs faster, (2.6 times smaller propagation time delay, and 1.85 times higher maximum frequency), and provides a better energy efficiency (67.9% saving), when compared with the dynamic domino CMOS logic style. The 18-bit high speed FTL, working at its maximum frequency, outperforms the dynamic domino logic in terms of the propagation delay (19.5 times less), maximum frequency (12.1 times more), and energy efficiency per bit (96.7% better).
ISBN: 9781424426058
DOI: 10.1109/ASSCC.2008.4708735
Source: Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 (4708735), p. 85-88
Appears in Collections:Actas de congresos
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