Identificador persistente para citar o vincular este elemento:
http://hdl.handle.net/10553/45097
| Título: | Speed-area-power optimization for DCFL and SDCFL class of logic using ring notation | Autores/as: | Eshraghian, K. Sarmiento, R Carballo, Pp Núñez, A. |
Clasificación UNESCO: | 3307 Tecnología electrónica | Palabras clave: | Semiconducting Gallium Arsenide Image processing Transistors, Field Effect Signal processing |
Fecha de publicación: | 1991 | Editor/a: | 0165-6074 | Publicación seriada: | Microprocessing and Microprogramming | Resumen: | Advances in the development of digital GaAs integrated circuits have progressed to the point that designers of signal and data processors can discern the system applications for which GaAs is best suited. Basic computation primitives in DSP and image processing systems are usually adders, multipliers and delay elements. In this paper we present the results of a systematic study conducted to evaluate the influence of layout and design methodologies, both conventional and innovative ones, on the performance of those DSP computation primitives. | URI: | http://hdl.handle.net/10553/45097 | ISSN: | 0165-6074 | DOI: | 10.1016/0165-6074(91)90326-O | Fuente: | Microprocessing And Microprogramming[ISSN 0165-6074],v. 32 (1-5), p. 75-82 |
| Colección: | Artículos |
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