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Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/45097
DC FieldValueLanguage
dc.contributor.authorEshraghian, K.en_US
dc.contributor.authorSarmiento, Ren_US
dc.contributor.authorCarballo, Ppen_US
dc.contributor.authorNúñez, A.en_US
dc.contributor.otherP. Carballo, Pedro-
dc.date.accessioned2018-11-22T07:14:41Z-
dc.date.available2018-11-22T07:14:41Z-
dc.date.issued1991en_US
dc.identifier.issn0165-6074en_US
dc.identifier.urihttp://hdl.handle.net/10553/45097-
dc.description.abstractAdvances in the development of digital GaAs integrated circuits have progressed to the point that designers of signal and data processors can discern the system applications for which GaAs is best suited. Basic computation primitives in DSP and image processing systems are usually adders, multipliers and delay elements. In this paper we present the results of a systematic study conducted to evaluate the influence of layout and design methodologies, both conventional and innovative ones, on the performance of those DSP computation primitives.en_US
dc.languageengen_US
dc.publisher0165-6074
dc.relation.ispartofMicroprocessing and Microprogrammingen_US
dc.sourceMicroprocessing And Microprogramming[ISSN 0165-6074],v. 32 (1-5), p. 75-82en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject.otherSemiconducting Gallium Arsenideen_US
dc.subject.otherImage processingen_US
dc.subject.otherTransistors, Field Effecten_US
dc.subject.otherSignal processingen_US
dc.titleSpeed-area-power optimization for DCFL and SDCFL class of logic using ring notationen_US
dc.typeinfo:eu-repo/semantics/Articleen_US
dc.typeArticleen_US
dc.identifier.doi10.1016/0165-6074(91)90326-Oen_US
dc.identifier.scopus2-s2.0-0026203384-
dc.identifier.isiA1991GD70800017-
dcterms.isPartOfMicroprocessing And Microprogramming
dcterms.sourceMicroprocessing And Microprogramming[ISSN 0165-6074],v. 32 (1-5), p. 75-82
dc.contributor.authorscopusid7007041524-
dc.contributor.authorscopusid35609452100-
dc.contributor.authorscopusid6602499289-
dc.contributor.authorscopusid7103279517-
dc.description.lastpage82-
dc.description.firstpage75-
dc.relation.volume32-
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Artículoen_US
dc.identifier.wosWOS:A1991GD70800017-
dc.contributor.daisngid228382-
dc.contributor.daisngid30404478
dc.contributor.daisngid116294-
dc.contributor.daisngid3056889-
dc.contributor.daisngid33795-
dc.identifier.investigatorRIDF-6600-2014-
dc.utils.revisionSíen_US
dc.contributor.wosstandardWOS:ESHRAGHIAN, K
dc.contributor.wosstandardWOS:SARMIENTO, R
dc.contributor.wosstandardWOS:CARBALLO, PP
dc.contributor.wosstandardWOS:NUNEZ, A
dc.date.coverdateAgosto 1991
dc.identifier.ulpgcSíes
item.fulltextSin texto completo-
item.grantfulltextnone-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-4843-0507-
crisitem.author.orcid0000-0001-7912-8768-
crisitem.author.orcid0000-0003-1295-1594-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameSarmiento Rodríguez, Roberto-
crisitem.author.fullNamePérez Carballo, Pedro Francisco-
crisitem.author.fullNameNúñez Ordóñez, Antonio-
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