Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/45097
Title: Speed-area-power optimization for DCFL and SDCFL class of logic using ring notation
Authors: Eshraghian, K.
Sarmiento, R 
Carballo, Pp 
Núñez, A. 
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: Semiconducting Gallium Arsenide
Image processing
Transistors, Field Effect
Signal processing
Issue Date: 1991
Publisher: 0165-6074
Journal: Microprocessing and Microprogramming 
Abstract: Advances in the development of digital GaAs integrated circuits have progressed to the point that designers of signal and data processors can discern the system applications for which GaAs is best suited. Basic computation primitives in DSP and image processing systems are usually adders, multipliers and delay elements. In this paper we present the results of a systematic study conducted to evaluate the influence of layout and design methodologies, both conventional and innovative ones, on the performance of those DSP computation primitives.
URI: http://hdl.handle.net/10553/45097
ISSN: 0165-6074
DOI: 10.1016/0165-6074(91)90326-O
Source: Microprocessing And Microprogramming[ISSN 0165-6074],v. 32 (1-5), p. 75-82
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