Thermal resistance characterization for multifinger SOI-MOSFETs

Abstract

Thermal conductance in multifinger silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) is usually modeled at room temperature with a linear dependence on the total gate width, which is valid only when thermal coupling saturates. This paper presents a physically based model for calculating the thermal resistance of SOI-MOSFETs that accounts for progressive thermal coupling as the number of fingers increases and the substrate temperature. The model, extracted from a variety of gate geometries using the ac conductance method, correctly predicts the temperature rise in the device channel up to a substrate temperature of 150 °C. Finally, this simple thermal resistance model, which is applicable to nanometer-scale transistors, can easily be added to circuit simulators.