|Title:||Improving memory latency aware fetch policies for SMT processors||Authors:||Cazorla, Francisco J.
Fernández García, Enrique
|UNESCO Clasification:||3304 Tecnología de los ordenadores
330412 Dispositivos de control
Long Latency Loads
Load Miss Predictors
|Issue Date:||2003||Publisher:||Springer||Journal:||Lecture Notes in Computer Science||Conference:||5th International Symposium on High Performance Computing/3rd International Workshop on OpenMP: Experiences and Implementations (WOMPEI 2003)||Abstract:||In SMT processors several threads run simultaneously to increase available ILP, sharing but competing for resources. The instruction fetch policy plays a key role, determining how shared resources are allocated.When a thread experiences an L2 miss, critical resources can be monopolized for a long time choking the execution of the remaining threads. A primary task of the instruction fetch policy is to prevent this situation. In this paper we propose novel improved versions of the three best published policies addressing this problem. bur policies significantly enhance the original ones in throughput, and fairness, also reducing the energy consumption.||URI:||http://hdl.handle.net/10553/76991||ISBN:||978-3-540-20359-9||ISSN:||0302-9743||Source:||High Performance Computing. ISHPC 2003. Lecture Notes in Computer Science [ISSN 0302-9743], v. 2858, p. 70-85, (2003)|
|Appears in Collections:||Actas de congresos|
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