Improving memory latency aware fetch policies for SMT processors

Abstract

In SMT processors several threads run simultaneously to increase available ILP, sharing but competing for resources. The instruction fetch policy plays a key role, determining how shared resources are allocated.When a thread experiences an L2 miss, critical resources can be monopolized for a long time choking the execution of the remaining threads. A primary task of the instruction fetch policy is to prevent this situation. In this paper we propose novel improved versions of the three best published policies addressing this problem. bur policies significantly enhance the original ones in throughput, and fairness, also reducing the energy consumption.