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Title: A reconfigurable data cache for adaptive processors
Authors: Benitez, D. 
Moure, J. C.
Rexachs, D. I.
Luque, E.
UNESCO Clasification: 330406 Arquitectura de ordenadores
Issue Date: 2006
Journal: Lecture Notes in Computer Science 
Conference: 2nd International Workshop on Reconfigurable Computing 
2nd International Workshop on Applied Reconfigurable Computing, ARC 2006 
Abstract: Adaptive processors can exploit the different characteristics exhibited by program phases better than a fixed hardware. However, they may significantly degrade performance and/or energy consumption. In this paper, we describe a reconfigurable cache memory, which is efficiently applied to the L1 data cache of an embedded general-purpose processor. A realistic hardware/software methodology of run-time tuning and reconfiguration. of the cache is also proposed, which is based on a pattern-matching algorithm. It is used to identify the cache configuration and processor frequency when the programs data working-set changes. Considering a design scenario driven by the best product execution time x energy consumption, we show that power dissipation and energy consumption of a two-level cache hierarchy and the product time x energy can be reduced on average by 39%, 38% and 37% respectively, when compared with a non-adaptive embedded microarchitecture.
ISSN: 0302-9743
DOI: 10.1007/11802839_31
Source: Reconfigurable Computing: Architectures And Applications [ISSN 0302-9743], v. 3985, p. 230-242, (2006)
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