Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/72736
DC FieldValueLanguage
dc.contributor.authorBenitez, D.en_US
dc.contributor.authorMoure, J. C.en_US
dc.contributor.authorRexachs, D. I.en_US
dc.contributor.authorLuque, E.en_US
dc.date.accessioned2020-05-22T10:12:03Z-
dc.date.available2020-05-22T10:12:03Z-
dc.date.issued2006en_US
dc.identifier.issn0302-9743en_US
dc.identifier.otherWoS-
dc.identifier.urihttp://hdl.handle.net/10553/72736-
dc.description.abstractAdaptive processors can exploit the different characteristics exhibited by program phases better than a fixed hardware. However, they may significantly degrade performance and/or energy consumption. In this paper, we describe a reconfigurable cache memory, which is efficiently applied to the L1 data cache of an embedded general-purpose processor. A realistic hardware/software methodology of run-time tuning and reconfiguration. of the cache is also proposed, which is based on a pattern-matching algorithm. It is used to identify the cache configuration and processor frequency when the programs data working-set changes. Considering a design scenario driven by the best product execution time x energy consumption, we show that power dissipation and energy consumption of a two-level cache hierarchy and the product time x energy can be reduced on average by 39%, 38% and 37% respectively, when compared with a non-adaptive embedded microarchitecture.en_US
dc.languageengen_US
dc.relation.ispartofLecture Notes in Computer Scienceen_US
dc.sourceReconfigurable Computing: Architectures And Applications [ISSN 0302-9743], v. 3985, p. 230-242, (2006)en_US
dc.subject330406 Arquitectura de ordenadoresen_US
dc.titleA reconfigurable data cache for adaptive processorsen_US
dc.typeinfo:eu-repo/semantics/conferenceObjecten_US
dc.typeConference_Paperen_US
dc.relation.conference2nd International Workshop on Reconfigurable Computing-
dc.relation.conference2nd International Workshop on Applied Reconfigurable Computing, ARC 2006-
dc.identifier.doi10.1007/11802839_31en_US
dc.identifier.scopus33749038621-
dc.identifier.isi000240036500031-
dc.contributor.authorscopusid7003286582-
dc.contributor.authorscopusid57188672353-
dc.contributor.authorscopusid6506076654-
dc.contributor.authorscopusid7005407181-
dc.description.lastpage242en_US
dc.description.firstpage230en_US
dc.relation.volume3985en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Actas de congresosen_US
dc.contributor.daisngid4870907-
dc.contributor.daisngid1409473-
dc.contributor.daisngid541089-
dc.contributor.daisngid64985-
dc.description.numberofpages13en_US
dc.utils.revisionen_US
dc.contributor.wosstandardWOS:Benitez, D-
dc.contributor.wosstandardWOS:Moure, JC-
dc.contributor.wosstandardWOS:Rexachs, DI-
dc.contributor.wosstandardWOS:Luque, E-
dc.date.coverdateEnero 2006en_US
dc.identifier.conferenceidevents120517-
item.grantfulltextnone-
item.fulltextSin texto completo-
crisitem.event.eventsstartdate01-03-2006-
crisitem.event.eventsstartdate01-03-2006-
crisitem.event.eventsenddate03-03-2006-
crisitem.event.eventsenddate03-03-2006-
crisitem.author.deptDepartamento de Informática y Sistemas-
crisitem.author.deptSIANI: Modelización y Simulación Computacional-
crisitem.author.deptIU Sistemas Inteligentes y Aplicaciones Numéricas-
crisitem.author.orcid0000-0003-2952-2972-
crisitem.author.parentorgIU Sistemas Inteligentes y Aplicaciones Numéricas-
crisitem.author.fullNameBenítez Díaz, Domingo Juan-
crisitem.author.departamentoInformática y Sistemas-
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