Identificador persistente para citar o vincular este elemento:
http://hdl.handle.net/10553/52228
| Campo DC | Valor | idioma |
|---|---|---|
| dc.contributor.author | Celinski, P. | en_US |
| dc.contributor.author | López Feliciano, José Francisco | en_US |
| dc.contributor.author | Al-Sarawi, S. | en_US |
| dc.contributor.author | Abbott, D. | en_US |
| dc.date.accessioned | 2018-11-25T18:31:09Z | - |
| dc.date.available | 2018-11-25T18:31:09Z | - |
| dc.date.issued | 2001 | en_US |
| dc.identifier.issn | 0013-5194 | en_US |
| dc.identifier.uri | http://hdl.handle.net/10553/52228 | - |
| dc.description.abstract | A new implementation of a threshold gate based on a capacitive input, charge recycling differential sense amplifier latch is presented. Simulation results indicate that the proposed structure has very low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations, and is therefore highly suitable as an element in digital integrated circuit design. | en_US |
| dc.language | spa | en_US |
| dc.publisher | 0013-5194 | |
| dc.relation.ispartof | Electronics letters | en_US |
| dc.source | Electronics Letters[ISSN 0013-5194],v. 37, p. 1067-1069 | en_US |
| dc.title | Low power, high speed, charge recycling CMOS threshold logic gate | en_US |
| dc.type | info:eu-repo/semantics/Article | en_US |
| dc.type | Article | en_US |
| dc.identifier.doi | 10.1049/el:20010742 | en_US |
| dc.identifier.scopus | 0035899234 | - |
| dc.identifier.isi | 000170989400007 | - |
| dc.contributor.authorscopusid | 6701421283 | - |
| dc.contributor.authorscopusid | 7404444793 | - |
| dc.contributor.authorscopusid | 7004170747 | - |
| dc.contributor.authorscopusid | 56053895400 | - |
| dc.description.lastpage | 1069 | en_US |
| dc.description.firstpage | 1067 | en_US |
| dc.relation.volume | 37 | en_US |
| dc.investigacion | Ingeniería y Arquitectura | en_US |
| dc.type2 | Artículo | en_US |
| dc.contributor.daisngid | 2345841 | - |
| dc.contributor.daisngid | 846472 | - |
| dc.contributor.daisngid | 256376 | - |
| dc.contributor.daisngid | 8183 | - |
| dc.utils.revision | Sí | en_US |
| dc.contributor.wosstandard | WOS:Celinski, P | - |
| dc.contributor.wosstandard | WOS:Lopez, JF | - |
| dc.contributor.wosstandard | WOS:Al-Sarawi, S | - |
| dc.contributor.wosstandard | WOS:Abbott, D | - |
| dc.date.coverdate | Agosto 2001 | en_US |
| dc.identifier.ulpgc | Sí | en_US |
| dc.contributor.buulpgc | BU-TEL | en_US |
| dc.description.jcr | 0,97 | |
| dc.description.jcrq | Q2 | |
| dc.description.scie | SCIE | |
| item.grantfulltext | none | - |
| item.fulltext | Sin texto completo | - |
| crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
| crisitem.author.dept | IU de Microelectrónica Aplicada | - |
| crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
| crisitem.author.orcid | 0000-0002-6304-2801 | - |
| crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
| crisitem.author.fullName | López Feliciano, José Francisco | - |
| Colección: | Artículos | |
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