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Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/52228
DC FieldValueLanguage
dc.contributor.authorCelinski, P.en_US
dc.contributor.authorLópez Feliciano, José Franciscoen_US
dc.contributor.authorAl-Sarawi, S.en_US
dc.contributor.authorAbbott, D.en_US
dc.date.accessioned2018-11-25T18:31:09Z-
dc.date.available2018-11-25T18:31:09Z-
dc.date.issued2001en_US
dc.identifier.issn0013-5194en_US
dc.identifier.urihttp://hdl.handle.net/10553/52228-
dc.description.abstractA new implementation of a threshold gate based on a capacitive input, charge recycling differential sense amplifier latch is presented. Simulation results indicate that the proposed structure has very low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations, and is therefore highly suitable as an element in digital integrated circuit design.en_US
dc.languagespaen_US
dc.publisher0013-5194
dc.relation.ispartofElectronics lettersen_US
dc.sourceElectronics Letters[ISSN 0013-5194],v. 37, p. 1067-1069en_US
dc.titleLow power, high speed, charge recycling CMOS threshold logic gateen_US
dc.typeinfo:eu-repo/semantics/Articleen_US
dc.typeArticleen_US
dc.identifier.doi10.1049/el:20010742en_US
dc.identifier.scopus0035899234-
dc.identifier.isi000170989400007-
dc.contributor.authorscopusid6701421283-
dc.contributor.authorscopusid7404444793-
dc.contributor.authorscopusid7004170747-
dc.contributor.authorscopusid56053895400-
dc.description.lastpage1069en_US
dc.description.firstpage1067en_US
dc.relation.volume37en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Artículoen_US
dc.contributor.daisngid2345841-
dc.contributor.daisngid846472-
dc.contributor.daisngid256376-
dc.contributor.daisngid8183-
dc.utils.revisionSíen_US
dc.contributor.wosstandardWOS:Celinski, P-
dc.contributor.wosstandardWOS:Lopez, JF-
dc.contributor.wosstandardWOS:Al-Sarawi, S-
dc.contributor.wosstandardWOS:Abbott, D-
dc.date.coverdateAgosto 2001en_US
dc.identifier.ulpgcSíen_US
dc.contributor.buulpgcBU-TELen_US
dc.description.jcr0,97
dc.description.jcrqQ2
dc.description.scieSCIE
item.grantfulltextnone-
item.fulltextSin texto completo-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-6304-2801-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameLópez Feliciano, José Francisco-
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