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http://hdl.handle.net/10553/47621
| Title: | Timimg model for SDCFL digital circuits | Authors: | Gómez, Luis Hernández Ballester, Antonio Núñez, Antonio |
UNESCO Clasification: | 3307 Tecnología electrónica | Keywords: | GaAs MESFET CMOS |
Issue Date: | 1992 | Publisher: | 0165-6074 | Journal: | Microprocessing and Microprogramming | Abstract: | In this work we present a timing analyzer suitable for dealing with GaAs MESFET SDCFL logic family and it uses inverters as an aproximation for multiple input gates. The model consists in an adaptation from a developed methodology for NMOS and CMOS Si logic families. The model has been validated against SPICE simulations. Measured errors are lower than 9%. © 1992. | URI: | http://hdl.handle.net/10553/47621 | ISSN: | 0165-6074 | DOI: | 10.1016/0165-6074(92)90132-Q | Source: | Microprocessing and Microprogramming[ISSN 0165-6074],v. 34, p. 193-196 |
| Appears in Collections: | Artículos |
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