Please use this identifier to cite or link to this item:
Title: Timimg model for SDCFL digital circuits
Authors: Gómez, Luis 
Hernández Ballester, Antonio 
Núñez, Antonio 
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: GaAs
Issue Date: 1992
Publisher: 0165-6074
Journal: Microprocessing and Microprogramming 
Abstract: In this work we present a timing analyzer suitable for dealing with GaAs MESFET SDCFL logic family and it uses inverters as an aproximation for multiple input gates. The model consists in an adaptation from a developed methodology for NMOS and CMOS Si logic families. The model has been validated against SPICE simulations. Measured errors are lower than 9%. © 1992.
ISSN: 0165-6074
DOI: 10.1016/0165-6074(92)90132-Q
Source: Microprocessing and Microprogramming[ISSN 0165-6074],v. 34, p. 193-196
Appears in Collections:Artículos
Show full item record

Google ScholarTM




Export metadata

Items in accedaCRIS are protected by copyright, with all rights reserved, unless otherwise indicated.