Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/47621
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dc.contributor.authorGómez, Luisen_US
dc.contributor.authorHernández Ballester, Antonioen_US
dc.contributor.authorNúñez, Antonioen_US
dc.date.accessioned2018-11-23T15:01:44Z-
dc.date.available2018-11-23T15:01:44Z-
dc.date.issued1992en_US
dc.identifier.issn0165-6074en_US
dc.identifier.urihttp://hdl.handle.net/10553/47621-
dc.description.abstractIn this work we present a timing analyzer suitable for dealing with GaAs MESFET SDCFL logic family and it uses inverters as an aproximation for multiple input gates. The model consists in an adaptation from a developed methodology for NMOS and CMOS Si logic families. The model has been validated against SPICE simulations. Measured errors are lower than 9%. © 1992.en_US
dc.languageengen_US
dc.publisher0165-6074-
dc.relation.ispartofMicroprocessing and Microprogrammingen_US
dc.sourceMicroprocessing and Microprogramming[ISSN 0165-6074],v. 34, p. 193-196en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject.otherGaAsen_US
dc.subject.otherMESFETen_US
dc.subject.otherCMOSen_US
dc.titleTimimg model for SDCFL digital circuitsen_US
dc.typeinfo:eu-repo/semantics/Articleen_US
dc.typeArticleen_US
dc.identifier.doi10.1016/0165-6074(92)90132-Qen_US
dc.identifier.scopus0026820816-
dc.contributor.authorscopusid56789548300-
dc.contributor.authorscopusid57194681887-
dc.contributor.authorscopusid7103279517-
dc.description.lastpage196en_US
dc.description.firstpage193en_US
dc.relation.volume34en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Artículoen_US
dc.utils.revisionen_US
dc.date.coverdateEnero 1992en_US
dc.identifier.ulpgces
item.grantfulltextnone-
item.fulltextSin texto completo-
crisitem.author.deptGIR Análisis Matemático de Imágenes y Gráficos por Ordenador-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0003-0667-2302-
crisitem.author.orcid0000-0003-1295-1594-
crisitem.author.parentorgDepartamento de Informática y Sistemas-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameGómez Déniz, Luis-
crisitem.author.fullNameHernández Ballester, Antonio-
crisitem.author.fullNameNúñez Ordóñez, Antonio-
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