Please use this identifier to cite or link to this item:
http://hdl.handle.net/10553/47621
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Gómez, Luis | en_US |
| dc.contributor.author | Hernández Ballester, Antonio | en_US |
| dc.contributor.author | Núñez, Antonio | en_US |
| dc.date.accessioned | 2018-11-23T15:01:44Z | - |
| dc.date.available | 2018-11-23T15:01:44Z | - |
| dc.date.issued | 1992 | en_US |
| dc.identifier.issn | 0165-6074 | en_US |
| dc.identifier.uri | http://hdl.handle.net/10553/47621 | - |
| dc.description.abstract | In this work we present a timing analyzer suitable for dealing with GaAs MESFET SDCFL logic family and it uses inverters as an aproximation for multiple input gates. The model consists in an adaptation from a developed methodology for NMOS and CMOS Si logic families. The model has been validated against SPICE simulations. Measured errors are lower than 9%. © 1992. | en_US |
| dc.language | eng | en_US |
| dc.publisher | 0165-6074 | - |
| dc.relation.ispartof | Microprocessing and Microprogramming | en_US |
| dc.source | Microprocessing and Microprogramming[ISSN 0165-6074],v. 34, p. 193-196 | en_US |
| dc.subject | 3307 Tecnología electrónica | en_US |
| dc.subject.other | GaAs | en_US |
| dc.subject.other | MESFET | en_US |
| dc.subject.other | CMOS | en_US |
| dc.title | Timimg model for SDCFL digital circuits | en_US |
| dc.type | info:eu-repo/semantics/Article | en_US |
| dc.type | Article | en_US |
| dc.identifier.doi | 10.1016/0165-6074(92)90132-Q | en_US |
| dc.identifier.scopus | 0026820816 | - |
| dc.contributor.authorscopusid | 56789548300 | - |
| dc.contributor.authorscopusid | 57194681887 | - |
| dc.contributor.authorscopusid | 7103279517 | - |
| dc.description.lastpage | 196 | en_US |
| dc.description.firstpage | 193 | en_US |
| dc.relation.volume | 34 | en_US |
| dc.investigacion | Ingeniería y Arquitectura | en_US |
| dc.type2 | Artículo | en_US |
| dc.utils.revision | Sí | en_US |
| dc.date.coverdate | Enero 1992 | en_US |
| dc.identifier.ulpgc | Sí | es |
| item.grantfulltext | none | - |
| item.fulltext | Sin texto completo | - |
| crisitem.author.dept | GIR IUCES: Centro de Tecnologías de la Imagen | - |
| crisitem.author.dept | IU de Cibernética, Empresa y Sociedad (IUCES) | - |
| crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
| crisitem.author.dept | GIR IUMA: Sistemas de Información y Comunicaciones | - |
| crisitem.author.dept | IU de Microelectrónica Aplicada | - |
| crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
| crisitem.author.dept | GIR IUMA: Sistemas de Información y Comunicaciones | - |
| crisitem.author.dept | IU de Microelectrónica Aplicada | - |
| crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
| crisitem.author.orcid | 0000-0003-0667-2302 | - |
| crisitem.author.orcid | 0000-0003-1295-1594 | - |
| crisitem.author.parentorg | IU de Cibernética, Empresa y Sociedad (IUCES) | - |
| crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
| crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
| crisitem.author.fullName | Gómez Déniz, Luis | - |
| crisitem.author.fullName | Hernández Ballester, Antonio | - |
| crisitem.author.fullName | Núñez Ordóñez, Antonio | - |
| Appears in Collections: | Artículos | |
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