|Title:||Gastim - A Timing Analyzer For Gaas Digital Circuits||Authors:||Hernández Ballester, Antonio
|UNESCO Clasification:||3307 Tecnología electrónica||Keywords:||Gallium arsenide
CMOS logic circuits
|Issue Date:||1993||Journal:||Euro-Dac 93 - European Design Automation Conference With Euro-Vhdl 93 : Proceedings||Conference:||Proceedings of the European Design Automation Conference||Abstract:||A methodology is presented to calculate delays in DCFL/SDCFL GaAs circuits. The model has been implemented in a prototype timing analyzer. Input slope influences and overlapping input transitions are taken into account. The simulation results show that the proposed model can predict the delay time withing 15% error and with a speed-up of three orders of magnitude for several circuits tested as compared with HSPICE simulations.||URI:||http://hdl.handle.net/10553/47617||ISBN:||0818643528||Source:||Euro-Dac 93 - European Design Automation Conference With Euro-Vhdl 93 : Proceedings, p. 190-195|
|Appears in Collections:||Actas de congresos|
checked on Feb 28, 2021
Items in accedaCRIS are protected by copyright, with all rights reserved, unless otherwise indicated.