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Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/47617
DC FieldValueLanguage
dc.contributor.authorHernández Ballester, Antonioen_US
dc.contributor.authorGomez, L.en_US
dc.contributor.authorNunez, A.en_US
dc.contributor.otherGomez, Luis-
dc.date.accessioned2018-11-23T14:59:55Z-
dc.date.available2018-11-23T14:59:55Z-
dc.date.issued1993en_US
dc.identifier.isbn0818643528en_US
dc.identifier.urihttp://hdl.handle.net/10553/47617-
dc.description.abstractA methodology is presented to calculate delays in DCFL/SDCFL GaAs circuits. The model has been implemented in a prototype timing analyzer. Input slope influences and overlapping input transitions are taken into account. The simulation results show that the proposed model can predict the delay time withing 15% error and with a speed-up of three orders of magnitude for several circuits tested as compared with HSPICE simulations.en_US
dc.languageengen_US
dc.relation.ispartofEuro-Dac 93 - European Design Automation Conference With Euro-Vhdl 93 : Proceedingsen_US
dc.sourceEuro-Dac 93 - European Design Automation Conference With Euro-Vhdl 93 : Proceedings, p. 190-195en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject.otherGallium arsenideen_US
dc.subject.otherDigital circuitsen_US
dc.subject.otherLogic devicesen_US
dc.subject.otherMESFETsen_US
dc.subject.otherCMOS logic circuitsen_US
dc.subject.otherPulse invertersen_US
dc.subject.otherLogic circuitsen_US
dc.titleGastim - A Timing Analyzer For Gaas Digital Circuitsen_US
dc.typeinfo:eu-repo/semantics/conferenceObjecten_US
dc.typeConferenceObjecten_US
dc.relation.conferenceProceedings of the European Design Automation Conferenceen_US
dc.identifier.scopus0027812470-
dc.identifier.isiA1993BZ20T00030-
dcterms.isPartOfEuro-Dac 93 - European Design Automation Conference With Euro-Vhdl 93 : Proceedings-
dcterms.sourceEuro-Dac 93 - European Design Automation Conference With Euro-Vhdl 93 : Proceedings, p. 190-195-
dc.contributor.authorscopusid57194681887-
dc.contributor.authorscopusid56789548300-
dc.contributor.authorscopusid7103279517-
dc.description.lastpage195en_US
dc.description.firstpage190en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Actas de congresosen_US
dc.identifier.wosWOS:A1993BZ20T00030-
dc.contributor.daisngid26070319-
dc.contributor.daisngid746480-
dc.contributor.daisngid33795-
dc.identifier.investigatorRIDK-7777-2014-
dc.utils.revisionSíen_US
dc.date.coverdateDiciembre 1993en_US
dc.identifier.ulpgcSíes
item.fulltextSin texto completo-
item.grantfulltextnone-
crisitem.author.deptGIR IUMA: Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUCES: Centro de Tecnologías de la Imagen-
crisitem.author.deptIU de Cibernética, Empresa y Sociedad (IUCES)-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0003-0667-2302-
crisitem.author.orcid0000-0003-1295-1594-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Cibernética, Empresa y Sociedad (IUCES)-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameHernández Ballester, Antonio-
crisitem.author.fullNameGómez Déniz, Luis-
crisitem.author.fullNameNúñez Ordóñez, Antonio-
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