Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/46933
Title: Power model for DCFL family
Authors: García, J. 
Hernández, A. 
Del Pino, J. 
Sendra, J. R. 
González, B. 
Nunez, A. 
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: direct coupled FET logic
field effect logic circuits
JFET integrated circuits
gallium arsenide
power consumption, et al
Issue Date: 2002
Publisher: 0013-5194
Journal: Electronics letters 
Abstract: A model to estimate power consumption in GaAs direct coupled FET logic (DCFL) family, which is based on sensitivity computations, is reported. Comparisons against SPICE simulations show errors smaller than 5% in power consumption estimation, while CPU time is reduced by more than two orders of magnitude.
URI: http://hdl.handle.net/10553/46933
ISSN: 0013-5194
DOI: 10.1049/el:20020027
Source: Electronics Letters[ISSN 0013-5194],v. 38, p. 13-14
Appears in Collections:Artículos
Show full item record

Page view(s)

31
checked on May 16, 2021

Google ScholarTM

Check

Altmetric


Share



Export metadata



Items in accedaCRIS are protected by copyright, with all rights reserved, unless otherwise indicated.