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Title: High-level design using Intel FPGA OpenCL: A hyperspectral imaging spatial-spectral classifier
Authors: Domingo, R.
Salvador, R.
Fabelo, H. 
Madronal, D.
Ortega, S. 
Lazcano, R.
Juarez, E.
Callico, G. 
Sanz, C.
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: Field programmable gate arrays
Parallel processing
Performance evaluation
Issue Date: 2017
Conference: 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2017 
Abstract: Current computational demands require increasing designer's efficiency and system performance per watt. A broadly accepted solution for efficient accelerators implementation is reconfigurable computing. However, typical HDL methodologies require very specific skills and a considerable amount of designer's time. Despite the new approaches to high-level synthesis like OpenCL, given the large heterogeneity in today's devices (manycore, CPUs, GPUs, FPGAs), there is no one-fits-all solution, so to maximize performance, platform-driven optimization is needed. This paper reviews some latest works using Intel FPGA SDK for OpenCL and the strategies for optimization, evaluating the framework for the design of a hyperspectral image spatial-spectral classifier accelerator. Results are reported for a Cyclone V SoC using Intel FPGA OpenCL Offline Compiler 16.0 out-of-the-box. From a common baseline C implementation running on the embedded ARM ® Cortex ® -A9, OpenCL-based synthesis is evaluated applying different generic and vendor specific optimizations. Results show how reasonable speedups are obtained in a device with scarce computing and embedded memory resources. It seems a great step has been given to effectively raise the abstraction level, but still, a considerable amount of HW design skills is needed.
ISBN: 9781538633441
DOI: 10.1109/ReCoSoC.2017.8016152
Source: 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2017 - Proceedings (8016152)
Appears in Collections:Actas de congresos
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