Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/46811
DC FieldValueLanguage
dc.contributor.authorDomingo, R.en_US
dc.contributor.authorSalvador, R.en_US
dc.contributor.authorFabelo, H.en_US
dc.contributor.authorMadronal, D.en_US
dc.contributor.authorOrtega, S.en_US
dc.contributor.authorLazcano, R.en_US
dc.contributor.authorJuarez, E.en_US
dc.contributor.authorCallico, G.en_US
dc.contributor.authorSanz, C.en_US
dc.date.accessioned2018-11-23T08:27:19Z-
dc.date.available2018-11-23T08:27:19Z-
dc.date.issued2017en_US
dc.identifier.isbn9781538633441en_US
dc.identifier.urihttp://hdl.handle.net/10553/46811-
dc.description.abstractCurrent computational demands require increasing designer's efficiency and system performance per watt. A broadly accepted solution for efficient accelerators implementation is reconfigurable computing. However, typical HDL methodologies require very specific skills and a considerable amount of designer's time. Despite the new approaches to high-level synthesis like OpenCL, given the large heterogeneity in today's devices (manycore, CPUs, GPUs, FPGAs), there is no one-fits-all solution, so to maximize performance, platform-driven optimization is needed. This paper reviews some latest works using Intel FPGA SDK for OpenCL and the strategies for optimization, evaluating the framework for the design of a hyperspectral image spatial-spectral classifier accelerator. Results are reported for a Cyclone V SoC using Intel FPGA OpenCL Offline Compiler 16.0 out-of-the-box. From a common baseline C implementation running on the embedded ARM ® Cortex ® -A9, OpenCL-based synthesis is evaluated applying different generic and vendor specific optimizations. Results show how reasonable speedups are obtained in a device with scarce computing and embedded memory resources. It seems a great step has been given to effectively raise the abstraction level, but still, a considerable amount of HW design skills is needed.en_US
dc.languageengen_US
dc.source12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2017 - Proceedings (8016152)en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject.otherField programmable gate arraysen_US
dc.subject.otherParallel processingen_US
dc.subject.otherKernelen_US
dc.subject.otherOptimizationen_US
dc.subject.otherPerformance evaluationen_US
dc.titleHigh-level design using Intel FPGA OpenCL: A hyperspectral imaging spatial-spectral classifieren_US
dc.typeinfo:eu-repo/semantics/conferenceObjecten_US
dc.typeConferenceObjecten_US
dc.relation.conference12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2017
dc.identifier.doi10.1109/ReCoSoC.2017.8016152
dc.identifier.scopus85030649024-
dc.contributor.authorscopusid57207567460-
dc.contributor.authorscopusid23005852100-
dc.contributor.authorscopusid56405568500-
dc.contributor.authorscopusid57192829417-
dc.contributor.authorscopusid57189334144-
dc.contributor.authorscopusid57192839213-
dc.contributor.authorscopusid36447485600-
dc.contributor.authorscopusid56006321500-
dc.contributor.authorscopusid7006751614-
dc.identifier.issue8016152-
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Actas de congresosen_US
dc.utils.revisionen_US
dc.date.coverdateAgosto 2017
dc.identifier.conferenceidevents121125
dc.identifier.ulpgces
item.fulltextCon texto completo-
item.grantfulltextopen-
crisitem.author.deptIUMA Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-9794-490X-
crisitem.author.orcid0000-0002-7519-954X-
crisitem.author.orcid0000-0002-3784-5504-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameFabelo Gómez, Himar Antonio-
crisitem.author.fullNameOrtega Sarmiento, Samuel-
crisitem.author.fullNameMarrero Callicó, Gustavo Iván-
crisitem.event.eventsstartdate12-07-2017-
crisitem.event.eventsenddate14-07-2017-
Appears in Collections:Actas de congresos
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