Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/45371
Title: Low power voltage limiter design for a full passive UHF RFID sensor
Authors: Fernández, E.
Beriain, A.
Solar, H.
García-Alonso, A.
Berenguer, R.
Sosa, J. 
Monzón, J. M. 
García-Alonso, Santiago 
Montiel-Nelson, J. A. 
UNESCO Clasification: 3306 Ingeniería y tecnología eléctricas
3325 Tecnología de las telecomunicaciones
Keywords: Solids
EPROM
Oscilloscopes
Demodulation
Clocks
Issue Date: 2011
Publisher: 1548-3746
Journal: Midwest Symposium on Circuits and Systems 
Conference: 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 
Abstract: This paper presents a low power voltage limiter design that avoids possible damages in the circuits of the analog front-end of the RFID sensor due to voltage surges whenever reader and tag are very close. The proposed voltage limiter design takes advantage of the implemented bandgap reference and voltage regulator in order to provide low temperature and process deviation of the limiting voltage. The measured limiting voltage is 2.9V with a voltage variation of only +/-0.025V for the four measured dies. The current consumption is only 150nA when the reader and the tag are far away one to each other, not limiting the sensitivity of the tag due to an undesired consumption in the voltage limiter. The circuit is implemented on a low cost 2P4M 0.35μm CMOS technology.
URI: http://hdl.handle.net/10553/45371
ISBN: 9781612848570
ISSN: 1548-3746
DOI: 10.1109/MWSCAS.2011.6026504
Source: Midwest Symposium on Circuits and Systems [ISSN 1548-3746] (6026504)
Appears in Collections:Actas de congresos
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