Low power voltage limiter design for a full passive UHF RFID sensor

Abstract

This paper presents a low power voltage limiter design that avoids possible damages in the circuits of the analog front-end of the RFID sensor due to voltage surges whenever reader and tag are very close. The proposed voltage limiter design takes advantage of the implemented bandgap reference and voltage regulator in order to provide low temperature and process deviation of the limiting voltage. The measured limiting voltage is 2.9V with a voltage variation of only +/-0.025V for the four measured dies. The current consumption is only 150nA when the reader and the tag are far away one to each other, not limiting the sensitivity of the tag due to an undesired consumption in the voltage limiter. The circuit is implemented on a low cost 2P4M 0.35μm CMOS technology.